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author | Gabe Black <gblack@eecs.umich.edu> | 2007-03-13 16:13:21 +0000 |
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committer | Gabe Black <gblack@eecs.umich.edu> | 2007-03-13 16:13:21 +0000 |
commit | ce18d900a17cdda2cc041b51c56e6c84fb155331 (patch) | |
tree | d7be0cac19e550c93fc207e749ea80e1cf9a639e /src/cpu/simple/base.hh | |
parent | 8edc9d79cee3edd6d16a8254a0180aaa242974c7 (diff) | |
download | gem5-ce18d900a17cdda2cc041b51c56e6c84fb155331.tar.xz |
Replaced makeExtMI with predecode.
Removed the getOpcode function from StaticInst which only made sense for Alpha.
Started implementing the x86 predecoder.
--HG--
extra : convert_revision : a13ea257c8943ef25e9bc573024a99abacf4a70d
Diffstat (limited to 'src/cpu/simple/base.hh')
-rw-r--r-- | src/cpu/simple/base.hh | 6 |
1 files changed, 4 insertions, 2 deletions
diff --git a/src/cpu/simple/base.hh b/src/cpu/simple/base.hh index 980ea2f96..10787c474 100644 --- a/src/cpu/simple/base.hh +++ b/src/cpu/simple/base.hh @@ -74,7 +74,6 @@ namespace Trace { class BaseSimpleCPU : public BaseCPU { protected: - typedef TheISA::MachInst MachInst; typedef TheISA::MiscReg MiscReg; typedef TheISA::FloatReg FloatReg; typedef TheISA::FloatRegBits FloatRegBits; @@ -122,7 +121,10 @@ class BaseSimpleCPU : public BaseCPU #endif // current instruction - MachInst inst; + TheISA::MachInst inst; + + // current extended machine instruction + TheISA::ExtMachInst extMachInst; // Static data storage TheISA::LargestRead dataReg; |