gem5 - gem5

Age	Commit message (Expand)	Author
2018-06-11	misc: Using smart pointers for memory Requests	Giacomo Travaglini
2018-06-11	misc: Substitute pointer to Request with aliased RequestPtr	Giacomo Travaglini
2016-08-15	cpu, arch: fix the type used for the request flags	Nikos Nikoleris
2016-01-17	cpu. arch: add initiateMemRead() to ExecContext interface	Steve Reinhardt
2015-10-12	misc: Add explicit overrides and fix other clang >= 3.5 issues	Andreas Hansson
2015-10-12	misc: Remove redundant compiler-specific defines	Andreas Hansson
2015-09-30	cpu,isa,mem: Add per-thread wakeup logic	Mitch Hayenga
2015-09-30	config,cpu: Add SMT support to Atomic and Timing CPUs	Mitch Hayenga
2015-07-28	revert 5af8f40d8f2c	Nilay Vaish
2015-07-26	cpu: implements vector registers	Nilay Vaish
2015-07-07	sim: Refactor the serialization base class	Andreas Sandberg
2015-02-16	arch: Make readMiscRegNoEffect const throughout	Andreas Hansson
2015-01-25	cpu: Remove all notion that we know when the cpu is misspeculating.	Ali Saidi
2014-11-14	arm: Fixes based on UBSan and static analysis	Andreas Hansson
2014-11-06	x86 isa: This patch attempts an implementation at mwait.	Marc Orr
2014-09-20	cpu: Remove unused deallocateContext calls	Mitch Hayenga
2014-09-19	arch: Pass faults by const reference where possible	Andreas Hansson
2014-09-03	arch, cpu: Factor out the ExecContext into a proper base class	Andreas Sandberg
2014-05-09	cpu: add more instruction mix statistics	Curtis Dunham
2014-02-09	cpu: simple: Add support for using branch predictors	Andreas Sandberg
2013-10-15	cpu: add a condition-code register class	Yasuko Eckert
2013-10-15	cpu: rename _DepTag constants to _Reg_Base	Steve Reinhardt
2013-01-12	x86: Changes to decoder, corrects 9376	Nilay Vaish
2013-01-07	cpu: Unify the serialization code for all of the CPU models	Andreas Sandberg
2012-05-26	CPU: Merge the predecoder and decoder.	Gabe Black
2012-05-25	Decode: Make the Decoder class defined per ISA.	Gabe Black
2012-03-09	CheckerCPU: Make CheckerCPU runtime selectable instead of compile selectable	Geoffrey Blake
2012-02-24	CPU: Round-two unifying instr/data CPU ports across models	Andreas Hansson
2012-02-12	cpu: add separate stats for insts/ops both globally and per cpu model	Anthony Gutierrez
2012-01-31	Merge with head, hopefully the last time for this batch.	Gabe Black
2012-01-31	clang: Enable compiling gem5 using clang 2.9 and 3.0	Koan-Sin Tan
2012-01-31	CheckerCPU: Re-factor CheckerCPU to be compatible with current gem5	Geoffrey Blake
2012-01-29	Implement Ali's review feedback.	Gabe Black
2011-11-01	SE/FS: Expose the same methods on the CPUs in SE and FS modes.	Gabe Black
2011-09-19	Syscall: Make the syscall function available in both SE and FS modes.	Gabe Black
2011-09-09	Decode: Pull instruction decoding out of the StaticInst class into its own.	Gabe Black
2011-05-04	CPU: Fix a case where timing simple cpu faults can nest.	Ali Saidi
2011-04-15	includes: sort all includes	Nathan Binkert
2011-02-06	mcpat: Adds McPAT performance counters	Joel Hestness
2010-12-07	O3: Make all instructions that write a misc. register not perform the write u...	Giacomo Gabrielli
2010-11-15	O3: Make O3 support variably lengthed instructions.	Gabe Black
2010-11-08	ARM/Alpha/Cpu: Change prefetchs to be more like normal loads.	Ali Saidi
2010-10-31	ISA,CPU,etc: Create an ISA defined PC type that abstracts out ISA behaviors.	Gabe Black
2010-08-31	CPU: Get rid of the unused ev5_trap function on the simple and checker CPUs.	Gabe Black
2010-08-23	CPU: Make Exec trace to print predication result (if false) for memory instru...	Min Kyu Jeong
2010-08-23	ARM/O3: store the result of the predicate evaluation in DynInst or Threadstate.	Min Kyu Jeong
2010-06-03	Minor remote GDB cleanup.	Steve Reinhardt
2010-03-23	cpu: fix exec tracing memory corruption bug	Steve Reinhardt
2009-09-23	arch: nuke arch/isa_specific.hh and move stuff to generated config/the_isa.hh	Nathan Binkert
2009-07-08	Registers: Get rid of the float register width parameter.	Gabe Black