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authorAnouk Van Laer <anouk.vanlaer@arm.com>2017-03-17 12:02:00 +0000
committerAndreas Sandberg <andreas.sandberg@arm.com>2017-11-20 11:03:03 +0000
commitc0d613adb4eca09c32aca1cc90f04c29574f69c6 (patch)
tree1c2a0d26778d8b8ca3f0b359f990dc695156bf8f /src/cpu/simple/timing.cc
parentd626f4f7aaa4d2c9f7ae1afc35577fa025b4de38 (diff)
downloadgem5-c0d613adb4eca09c32aca1cc90f04c29574f69c6.tar.xz
pwr: Adds logic to enter power gating for the cpu model
If the CPU has been clock gated for a sufficient amount of time (configurable via pwrGatingLatency), the CPU will go into the OFF power state. This does not model hardware, just behaviour. Change-Id: Ib3681d1ffa6ad25eba60f47b4020325f63472d43 Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/3969 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Diffstat (limited to 'src/cpu/simple/timing.cc')
-rw-r--r--src/cpu/simple/timing.cc8
1 files changed, 7 insertions, 1 deletions
diff --git a/src/cpu/simple/timing.cc b/src/cpu/simple/timing.cc
index d2cb6ee21..f57354d56 100644
--- a/src/cpu/simple/timing.cc
+++ b/src/cpu/simple/timing.cc
@@ -1,6 +1,6 @@
/*
* Copyright 2014 Google, Inc.
- * Copyright (c) 2010-2013,2015 ARM Limited
+ * Copyright (c) 2010-2013,2015,2017 ARM Limited
* All rights reserved
*
* The license below extends only to copyright in the software and shall
@@ -94,6 +94,9 @@ TimingSimpleCPU::~TimingSimpleCPU()
DrainState
TimingSimpleCPU::drain()
{
+ // Deschedule any power gating event (if any)
+ deschedulePowerGatingEvent();
+
if (switchedOut())
return DrainState::Drained;
@@ -146,6 +149,9 @@ TimingSimpleCPU::drainResume()
}
}
+ // Reschedule any power gating event (if any)
+ schedulePowerGatingEvent();
+
system->totalNumInsts = 0;
}