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authorGabe Black <gblack@eecs.umich.edu>2006-10-31 02:08:44 -0500
committerGabe Black <gblack@eecs.umich.edu>2006-10-31 02:08:44 -0500
commit4862879a9420c52d48532d957b616c458b643a1e (patch)
tree576a3c724920ede579d5f9fe7ec52e41911a306a /src/cpu/simple
parent79d4bede429bb5c3413fcd0cfe6f2d1790c8312d (diff)
downloadgem5-4862879a9420c52d48532d957b616c458b643a1e.tar.xz
Put the Alpha tlb stuff into the AlphaISA namespace, and give the classes more neutral names.
--HG-- extra : convert_revision : 702c715b7516a16602172deb1b78d6a7ab848fd4
Diffstat (limited to 'src/cpu/simple')
-rw-r--r--src/cpu/simple/atomic.cc4
-rw-r--r--src/cpu/simple/base.hh11
-rw-r--r--src/cpu/simple/timing.cc4
3 files changed, 11 insertions, 8 deletions
diff --git a/src/cpu/simple/atomic.cc b/src/cpu/simple/atomic.cc
index 11e4d2acb..1e12aadef 100644
--- a/src/cpu/simple/atomic.cc
+++ b/src/cpu/simple/atomic.cc
@@ -513,8 +513,8 @@ BEGIN_DECLARE_SIM_OBJECT_PARAMS(AtomicSimpleCPU)
Param<int> cpu_id;
#if FULL_SYSTEM
- SimObjectParam<AlphaITB *> itb;
- SimObjectParam<AlphaDTB *> dtb;
+ SimObjectParam<TheISA::ITB *> itb;
+ SimObjectParam<TheISA::DTB *> dtb;
Param<Tick> profile;
#else
SimObjectParam<Process *> workload;
diff --git a/src/cpu/simple/base.hh b/src/cpu/simple/base.hh
index af6b6f835..1a9fc5127 100644
--- a/src/cpu/simple/base.hh
+++ b/src/cpu/simple/base.hh
@@ -47,8 +47,11 @@
// forward declarations
#if FULL_SYSTEM
class Processor;
-class AlphaITB;
-class AlphaDTB;
+namespace TheISA
+{
+ class ITB;
+ class DTB;
+}
class MemObject;
class RemoteGDB;
@@ -97,8 +100,8 @@ class BaseSimpleCPU : public BaseCPU
{
MemObject *mem;
#if FULL_SYSTEM
- AlphaITB *itb;
- AlphaDTB *dtb;
+ TheISA::ITB *itb;
+ TheISA::DTB *dtb;
#else
Process *process;
#endif
diff --git a/src/cpu/simple/timing.cc b/src/cpu/simple/timing.cc
index fe6775ea4..438417882 100644
--- a/src/cpu/simple/timing.cc
+++ b/src/cpu/simple/timing.cc
@@ -665,8 +665,8 @@ BEGIN_DECLARE_SIM_OBJECT_PARAMS(TimingSimpleCPU)
Param<int> cpu_id;
#if FULL_SYSTEM
- SimObjectParam<AlphaITB *> itb;
- SimObjectParam<AlphaDTB *> dtb;
+ SimObjectParam<TheISA::ITB *> itb;
+ SimObjectParam<TheISA::DTB *> dtb;
Param<Tick> profile;
#else
SimObjectParam<Process *> workload;