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| author | Steve Reinhardt <stever@eecs.umich.edu> | 2006-05-26 13:48:35 -0400 |
|---|---|---|
| committer | Steve Reinhardt <stever@eecs.umich.edu> | 2006-05-26 13:48:35 -0400 |
| commit | da6a7b1263cf624790f06a5f944366fb113dffc8 (patch) | |
| tree | 16110f2f8efa8b98a42d3b85c43a3a7b8ae1f1ce /src/cpu/simple | |
| parent | cf826ae296a4277bdf2ce46e4484295efde5a3c2 (diff) | |
| download | gem5-da6a7b1263cf624790f06a5f944366fb113dffc8.tar.xz | |
Add names to memory Port objects for tracing.
--HG--
extra : convert_revision : ddf30084e343e8656e4812ab20356292b35507ee
Diffstat (limited to 'src/cpu/simple')
| -rw-r--r-- | src/cpu/simple/atomic.cc | 2 | ||||
| -rw-r--r-- | src/cpu/simple/atomic.hh | 4 | ||||
| -rw-r--r-- | src/cpu/simple/timing.hh | 8 |
3 files changed, 7 insertions, 7 deletions
diff --git a/src/cpu/simple/atomic.cc b/src/cpu/simple/atomic.cc index e9422b9c0..04a84c92a 100644 --- a/src/cpu/simple/atomic.cc +++ b/src/cpu/simple/atomic.cc @@ -117,7 +117,7 @@ AtomicSimpleCPU::CpuPort::recvRetry() AtomicSimpleCPU::AtomicSimpleCPU(Params *p) : BaseSimpleCPU(p), tickEvent(this), width(p->width), simulate_stalls(p->simulate_stalls), - icachePort(this), dcachePort(this) + icachePort(name() + "-iport", this), dcachePort(name() + "-iport", this) { _status = Idle; diff --git a/src/cpu/simple/atomic.hh b/src/cpu/simple/atomic.hh index d0ba085f0..ab3a3e8ef 100644 --- a/src/cpu/simple/atomic.hh +++ b/src/cpu/simple/atomic.hh @@ -84,8 +84,8 @@ class AtomicSimpleCPU : public BaseSimpleCPU public: - CpuPort(AtomicSimpleCPU *_cpu) - : cpu(_cpu) + CpuPort(const std::string &_name, AtomicSimpleCPU *_cpu) + : Port(_name), cpu(_cpu) { } protected: diff --git a/src/cpu/simple/timing.hh b/src/cpu/simple/timing.hh index 83be025d9..7f38e629a 100644 --- a/src/cpu/simple/timing.hh +++ b/src/cpu/simple/timing.hh @@ -71,8 +71,8 @@ class TimingSimpleCPU : public BaseSimpleCPU public: - CpuPort(TimingSimpleCPU *_cpu) - : cpu(_cpu) + CpuPort(const std::string &_name, TimingSimpleCPU *_cpu) + : Port(_name), cpu(_cpu) { } protected: @@ -93,7 +93,7 @@ class TimingSimpleCPU : public BaseSimpleCPU public: IcachePort(TimingSimpleCPU *_cpu) - : CpuPort(_cpu) + : CpuPort(_cpu->name() + "-iport", _cpu) { } protected: @@ -108,7 +108,7 @@ class TimingSimpleCPU : public BaseSimpleCPU public: DcachePort(TimingSimpleCPU *_cpu) - : CpuPort(_cpu) + : CpuPort(_cpu->name() + "-dport", _cpu) { } protected: |