diff options
| author | Gabe Black <gabeblack@google.com> | 2019-08-17 01:40:39 -0700 |
|---|---|---|
| committer | Gabe Black <gabeblack@google.com> | 2019-08-28 08:25:51 +0000 |
| commit | 7584c390ebbb890642468a7cfd40aaa52699684e (patch) | |
| tree | 205c6735a3a8460249dfe57308996cab06e811a3 /src/cpu/simple | |
| parent | 642489740985f2804e8229c69edeb46f2432d8f9 (diff) | |
| download | gem5-7584c390ebbb890642468a7cfd40aaa52699684e.tar.xz | |
cpu: Make get(Data|Inst)Port return a Port and not a MasterPort.
No caller uses any of the MasterPort specific properties of these
function's return values, so we can instead return a reference to the
base Port class. This makes it possible for the data and inst ports
to be of any port type, not just gem5 style MasterPorts. This makes
life simpler for, for example, systemc based CPUs which might have TLM
ports.
It also makes it possible for any two CPUs which have compatible ports
to be switched between, as long as the ports they use support being
unbound. Unfortunately that does not include TLM or systemc ports which
are bound permanently.
Change-Id: I98fce5a16d2ef1af051238e929dd96d57a4ac838
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/20240
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Gabe Black <gabeblack@google.com>
Diffstat (limited to 'src/cpu/simple')
| -rw-r--r-- | src/cpu/simple/atomic.hh | 4 | ||||
| -rw-r--r-- | src/cpu/simple/timing.hh | 4 |
2 files changed, 4 insertions, 4 deletions
diff --git a/src/cpu/simple/atomic.hh b/src/cpu/simple/atomic.hh index ba52bc933..69ac09e4c 100644 --- a/src/cpu/simple/atomic.hh +++ b/src/cpu/simple/atomic.hh @@ -174,10 +174,10 @@ class AtomicSimpleCPU : public BaseSimpleCPU protected: /** Return a reference to the data port. */ - MasterPort &getDataPort() override { return dcachePort; } + Port &getDataPort() override { return dcachePort; } /** Return a reference to the instruction port. */ - MasterPort &getInstPort() override { return icachePort; } + Port &getInstPort() override { return icachePort; } /** Perform snoop for other cpu-local thread contexts. */ void threadSnoop(PacketPtr pkt, ThreadID sender); diff --git a/src/cpu/simple/timing.hh b/src/cpu/simple/timing.hh index e423ae8e2..53e0ed7e1 100644 --- a/src/cpu/simple/timing.hh +++ b/src/cpu/simple/timing.hh @@ -264,10 +264,10 @@ class TimingSimpleCPU : public BaseSimpleCPU protected: /** Return a reference to the data port. */ - MasterPort &getDataPort() override { return dcachePort; } + Port &getDataPort() override { return dcachePort; } /** Return a reference to the instruction port. */ - MasterPort &getInstPort() override { return icachePort; } + Port &getInstPort() override { return icachePort; } public: |