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authorGabe Black <gabeblack@google.com>2019-10-14 15:31:26 -0700
committerGabe Black <gabeblack@google.com>2019-10-25 22:42:31 +0000
commita2a8dac5c2a26e91432415f409b55f04cff9c2e4 (patch)
tree5cdd34c965e349953d361582923f6467fb209382 /src/cpu/simple
parentfd030fd9f5893e1ce198bf760ab4a7f2704d921b (diff)
downloadgem5-a2a8dac5c2a26e91432415f409b55f04cff9c2e4.tar.xz
cpu: Access inst events through ThreadContext instead of the CPU.
Also delete the CPU interface. Change-Id: I62a6b0a9a303d672f4083bdedf393f9f6d07331f Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/22109 Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Maintainer: Andreas Sandberg <andreas.sandberg@arm.com> Tested-by: kokoro <noreply+kokoro@google.com>
Diffstat (limited to 'src/cpu/simple')
-rw-r--r--src/cpu/simple/base.cc2
1 files changed, 1 insertions, 1 deletions
diff --git a/src/cpu/simple/base.cc b/src/cpu/simple/base.cc
index fc07fedc0..f45165b9e 100644
--- a/src/cpu/simple/base.cc
+++ b/src/cpu/simple/base.cc
@@ -500,7 +500,7 @@ BaseSimpleCPU::preExecute()
t_info.setMemAccPredicate(true);
// check for instruction-count-based events
- serviceInstCountEvents(curThread, t_info.numInst);
+ thread->getTC()->serviceInstCountEvents(t_info.numInst);
// decode the instruction
inst = gtoh(inst);