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| author | Giacomo Travaglini <giacomo.travaglini@arm.com> | 2019-01-04 16:20:49 +0000 |
|---|---|---|
| committer | Giacomo Travaglini <giacomo.travaglini@arm.com> | 2019-01-25 12:51:29 +0000 |
| commit | b045de7e6969d5a40d4a3f9b178844cc911ac4c2 (patch) | |
| tree | b850b77d7877a6133d1dc83edc2871edf517b46e /src/cpu/simple | |
| parent | e7c8154479b3d0dbdc26cbb91fbccc2b9870e394 (diff) | |
| download | gem5-b045de7e6969d5a40d4a3f9b178844cc911ac4c2.tar.xz | |
cpu: Fix VecElemClass bugs in cpu models
This patch is:
* Adding a missing VecElemClass entry
* Fixing assertion in rename map which was checking the number of free
vector registers rather than free vector element registers
* Fixing assertion in read/setVecElemOperand APIs.
* Using the right register index in SimpleThread
* Using VecElem instead of VecReg on O3 readArchVecElem
Change-Id: I265320dcbe35eb47075991301dfc99333c5190c4
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/15598
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Diffstat (limited to 'src/cpu/simple')
| -rw-r--r-- | src/cpu/simple/exec_context.hh | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/src/cpu/simple/exec_context.hh b/src/cpu/simple/exec_context.hh index 7db7d20d9..cbca34123 100644 --- a/src/cpu/simple/exec_context.hh +++ b/src/cpu/simple/exec_context.hh @@ -317,7 +317,7 @@ class SimpleExecContext : public ExecContext { readVecElemOperand(const StaticInst *si, int idx) const override { numVecRegReads++; - const RegId& reg = si->destRegIdx(idx); + const RegId& reg = si->srcRegIdx(idx); assert(reg.isVecElem()); return thread->readVecElem(reg); } |