diff options
| author | Andreas Hansson <andreas.hansson@arm.com> | 2012-07-09 12:35:39 -0400 |
|---|---|---|
| committer | Andreas Hansson <andreas.hansson@arm.com> | 2012-07-09 12:35:39 -0400 |
| commit | b265d9925c123f0df50db98cf56dab6a3596b54b (patch) | |
| tree | 2b115ce862733a499c453352db3a6ae5b9f93cd6 /src/cpu/simple | |
| parent | 1c2ee987f37f4aac16cd0ff3e3ceeff949066a94 (diff) | |
| download | gem5-b265d9925c123f0df50db98cf56dab6a3596b54b.tar.xz | |
Port: Align port names in C++ and Python
This patch is a first step to align the port names used in the Python
world and the C++ world. Ultimately it serves to make the use of
config.json together with output from the simulation easier, including
post-processing of statistics.
Most notably, the CPU, cache, and bus is addressed in this patch, and
there might be other ports that should be updated accordingly. The
dash name separator has also been replaced with a "." which is what is
used to concatenate the names in python, and a separation is made
between the master and slave port in the bus.
Diffstat (limited to 'src/cpu/simple')
| -rw-r--r-- | src/cpu/simple/atomic.cc | 3 | ||||
| -rw-r--r-- | src/cpu/simple/timing.hh | 5 |
2 files changed, 5 insertions, 3 deletions
diff --git a/src/cpu/simple/atomic.cc b/src/cpu/simple/atomic.cc index 0886b276f..fc6724939 100644 --- a/src/cpu/simple/atomic.cc +++ b/src/cpu/simple/atomic.cc @@ -105,7 +105,8 @@ AtomicSimpleCPU::AtomicSimpleCPU(AtomicSimpleCPUParams *p) : BaseSimpleCPU(p), tickEvent(this), width(p->width), locked(false), simulate_data_stalls(p->simulate_data_stalls), simulate_inst_stalls(p->simulate_inst_stalls), - icachePort(name() + "-iport", this), dcachePort(name() + "-iport", this), + icachePort(name() + ".icache_port", this), + dcachePort(name() + ".dcache_port", this), fastmem(p->fastmem) { _status = Idle; diff --git a/src/cpu/simple/timing.hh b/src/cpu/simple/timing.hh index 95edea0b6..b6b78c5db 100644 --- a/src/cpu/simple/timing.hh +++ b/src/cpu/simple/timing.hh @@ -178,7 +178,7 @@ class TimingSimpleCPU : public BaseSimpleCPU public: IcachePort(TimingSimpleCPU *_cpu) - : TimingCPUPort(_cpu->name() + "-iport", _cpu), + : TimingCPUPort(_cpu->name() + ".icache_port", _cpu), tickEvent(_cpu) { } @@ -206,7 +206,8 @@ class TimingSimpleCPU : public BaseSimpleCPU public: DcachePort(TimingSimpleCPU *_cpu) - : TimingCPUPort(_cpu->name() + "-dport", _cpu), tickEvent(_cpu) + : TimingCPUPort(_cpu->name() + ".dcache_port", _cpu), + tickEvent(_cpu) { } protected: |