cpu: Fix coding style (byteEnable->byte_enable)

Change-Id: I2206559c6c2a6e6a0452e9c7d9964792afa9f358
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/23282
Maintainer: Jason Lowe-Power <jason@lowepower.com>
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>

6 files changed, 27 insertions, 27 deletions

diff --git a/src/cpu/simple/atomic.cc b/src/cpu/simple/atomic.cc
index 9052cee2e..3e3ba41b3 100644
--- a/src/cpu/simple/atomic.cc
+++ b/src/cpu/simple/atomic.cc
@@ -371,7 +371,7 @@ AtomicSimpleCPU::genMemFragmentRequest(const RequestPtr& req, Addr frag_addr,
 Fault
 AtomicSimpleCPU::readMem(Addr addr, uint8_t * data, unsigned size,
                          Request::Flags flags,
-                         const std::vector<bool>& byteEnable)
+                         const std::vector<bool>& byte_enable)
 {
     SimpleExecContext& t_info = *threadInfo[curThread];
     SimpleThread* thread = t_info.thread;
@@ -394,7 +394,7 @@ AtomicSimpleCPU::readMem(Addr addr, uint8_t * data, unsigned size,
 
     while (1) {
         predicate = genMemFragmentRequest(req, frag_addr, size, flags,
-                                          byteEnable, frag_size, size_left);
+                                          byte_enable, frag_size, size_left);
 
         // translate to physical address
         if (predicate) {
@@ -453,7 +453,7 @@ AtomicSimpleCPU::readMem(Addr addr, uint8_t * data, unsigned size,
 Fault
 AtomicSimpleCPU::writeMem(uint8_t *data, unsigned size, Addr addr,
                           Request::Flags flags, uint64_t *res,
-                          const std::vector<bool>& byteEnable)
+                          const std::vector<bool>& byte_enable)
 {
     SimpleExecContext& t_info = *threadInfo[curThread];
     SimpleThread* thread = t_info.thread;
@@ -485,7 +485,7 @@ AtomicSimpleCPU::writeMem(uint8_t *data, unsigned size, Addr addr,
 
     while (1) {
         predicate = genMemFragmentRequest(req, frag_addr, size, flags,
-                                          byteEnable, frag_size, size_left);
+                                          byte_enable, frag_size, size_left);
 
         // translate to physical address
         if (predicate)
@@ -541,7 +541,7 @@ AtomicSimpleCPU::writeMem(uint8_t *data, unsigned size, Addr addr,
         if (fault != NoFault || size_left == 0)
         {
             if (req->isLockedRMW() && fault == NoFault) {
-                assert(byteEnable.empty());
+                assert(byte_enable.empty());
                 locked = false;
             }
 
diff --git a/src/cpu/simple/atomic.hh b/src/cpu/simple/atomic.hh
index 121cecd65..8fd950527 100644
--- a/src/cpu/simple/atomic.hh
+++ b/src/cpu/simple/atomic.hh
@@ -218,12 +218,12 @@ class AtomicSimpleCPU : public BaseSimpleCPU
 
     Fault readMem(Addr addr, uint8_t *data, unsigned size,
                   Request::Flags flags,
-                  const std::vector<bool>& byteEnable = std::vector<bool>())
+                  const std::vector<bool>& byte_enable = std::vector<bool>())
         override;
 
     Fault writeMem(uint8_t *data, unsigned size,
                    Addr addr, Request::Flags flags, uint64_t *res,
-                   const std::vector<bool>& byteEnable = std::vector<bool>())
+                   const std::vector<bool>& byte_enable = std::vector<bool>())
         override;
 
     Fault amoMem(Addr addr, uint8_t* data, unsigned size,
diff --git a/src/cpu/simple/base.hh b/src/cpu/simple/base.hh
index f8e534c85..32c20a1a0 100644
--- a/src/cpu/simple/base.hh
+++ b/src/cpu/simple/base.hh
@@ -144,19 +144,19 @@ class BaseSimpleCPU : public BaseCPU
 
     virtual Fault readMem(Addr addr, uint8_t* data, unsigned size,
                           Request::Flags flags,
-                          const std::vector<bool>& byteEnable =
+                          const std::vector<bool>& byte_enable =
                               std::vector<bool>())
     { panic("readMem() is not implemented\n"); }
 
     virtual Fault initiateMemRead(Addr addr, unsigned size,
                                   Request::Flags flags,
-                                  const std::vector<bool>& byteEnable =
+                                  const std::vector<bool>& byte_enable =
                                       std::vector<bool>())
     { panic("initiateMemRead() is not implemented\n"); }
 
     virtual Fault writeMem(uint8_t* data, unsigned size, Addr addr,
                            Request::Flags flags, uint64_t* res,
-                           const std::vector<bool>& byteEnable =
+                           const std::vector<bool>& byte_enable =
                                std::vector<bool>())
     { panic("writeMem() is not implemented\n"); }
 
diff --git a/src/cpu/simple/exec_context.hh b/src/cpu/simple/exec_context.hh
index 8e4aa3961..04be1a016 100644
--- a/src/cpu/simple/exec_context.hh
+++ b/src/cpu/simple/exec_context.hh
@@ -437,31 +437,31 @@ class SimpleExecContext : public ExecContext {
     Fault
     readMem(Addr addr, uint8_t *data, unsigned int size,
             Request::Flags flags,
-            const std::vector<bool>& byteEnable = std::vector<bool>())
+            const std::vector<bool>& byte_enable = std::vector<bool>())
         override
     {
-        assert(byteEnable.empty() || byteEnable.size() == size);
-        return cpu->readMem(addr, data, size, flags, byteEnable);
+        assert(byte_enable.empty() || byte_enable.size() == size);
+        return cpu->readMem(addr, data, size, flags, byte_enable);
     }
 
     Fault
     initiateMemRead(Addr addr, unsigned int size,
                     Request::Flags flags,
-                    const std::vector<bool>& byteEnable = std::vector<bool>())
+                    const std::vector<bool>& byte_enable = std::vector<bool>())
         override
     {
-        assert(byteEnable.empty() || byteEnable.size() == size);
-        return cpu->initiateMemRead(addr, size, flags, byteEnable);
+        assert(byte_enable.empty() || byte_enable.size() == size);
+        return cpu->initiateMemRead(addr, size, flags, byte_enable);
     }
 
     Fault
     writeMem(uint8_t *data, unsigned int size, Addr addr,
              Request::Flags flags, uint64_t *res,
-             const std::vector<bool>& byteEnable = std::vector<bool>())
+             const std::vector<bool>& byte_enable = std::vector<bool>())
         override
     {
-        assert(byteEnable.empty() || byteEnable.size() == size);
-        return cpu->writeMem(data, size, addr, flags, res, byteEnable);
+        assert(byte_enable.empty() || byte_enable.size() == size);
+        return cpu->writeMem(data, size, addr, flags, res, byte_enable);
     }
 
     Fault amoMem(Addr addr, uint8_t *data, unsigned int size,
diff --git a/src/cpu/simple/timing.cc b/src/cpu/simple/timing.cc
index d05eece27..6487ffa97 100644
--- a/src/cpu/simple/timing.cc
+++ b/src/cpu/simple/timing.cc
@@ -418,7 +418,7 @@ TimingSimpleCPU::buildSplitPacket(PacketPtr &pkt1, PacketPtr &pkt2,
 Fault
 TimingSimpleCPU::initiateMemRead(Addr addr, unsigned size,
                                  Request::Flags flags,
-                                 const std::vector<bool>& byteEnable)
+                                 const std::vector<bool>& byte_enable)
 {
     SimpleExecContext &t_info = *threadInfo[curThread];
     SimpleThread* thread = t_info.thread;
@@ -435,8 +435,8 @@ TimingSimpleCPU::initiateMemRead(Addr addr, unsigned size,
     RequestPtr req = std::make_shared<Request>(
         asid, addr, size, flags, dataMasterId(), pc,
         thread->contextId());
-    if (!byteEnable.empty()) {
-        req->setByteEnable(byteEnable);
+    if (!byte_enable.empty()) {
+        req->setByteEnable(byte_enable);
     }
 
     req->taskId(taskId());
@@ -496,7 +496,7 @@ TimingSimpleCPU::handleWritePacket()
 Fault
 TimingSimpleCPU::writeMem(uint8_t *data, unsigned size,
                           Addr addr, Request::Flags flags, uint64_t *res,
-                          const std::vector<bool>& byteEnable)
+                          const std::vector<bool>& byte_enable)
 {
     SimpleExecContext &t_info = *threadInfo[curThread];
     SimpleThread* thread = t_info.thread;
@@ -521,8 +521,8 @@ TimingSimpleCPU::writeMem(uint8_t *data, unsigned size,
     RequestPtr req = std::make_shared<Request>(
         asid, addr, size, flags, dataMasterId(), pc,
         thread->contextId());
-    if (!byteEnable.empty()) {
-        req->setByteEnable(byteEnable);
+    if (!byte_enable.empty()) {
+        req->setByteEnable(byte_enable);
     }
 
     req->taskId(taskId());
diff --git a/src/cpu/simple/timing.hh b/src/cpu/simple/timing.hh
index 27faa177a..cab4253fb 100644
--- a/src/cpu/simple/timing.hh
+++ b/src/cpu/simple/timing.hh
@@ -284,12 +284,12 @@ class TimingSimpleCPU : public BaseSimpleCPU
 
     Fault initiateMemRead(Addr addr, unsigned size,
             Request::Flags flags,
-            const std::vector<bool>& byteEnable =std::vector<bool>())
+            const std::vector<bool>& byte_enable =std::vector<bool>())
         override;
 
     Fault writeMem(uint8_t *data, unsigned size,
                    Addr addr, Request::Flags flags, uint64_t *res,
-                   const std::vector<bool>& byteEnable = std::vector<bool>())
+                   const std::vector<bool>& byte_enable = std::vector<bool>())
         override;
 
     Fault initiateMemAMO(Addr addr, unsigned size, Request::Flags flags,