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authorAndreas Sandberg <andreas.sandberg@arm.com>2019-01-25 14:26:21 +0000
committerAndreas Sandberg <andreas.sandberg@arm.com>2019-02-12 09:43:00 +0000
commitef71a987c1987f7543d3bf76ed9e5ce62f4d1daa (patch)
treec672aa096c0088820c7ffa341b2d603cef6f66d6 /src/cpu/simple
parent9fbfb45e51e657b364334a1c96ba23698d181edb (diff)
downloadgem5-ef71a987c1987f7543d3bf76ed9e5ce62f4d1daa.tar.xz
python: Don't assume SimObjects live in the global namespace
The importer in Python 3 doesn't like the way we import SimObjects from the global namespace. Convert the existing SimObject declarations to import from m5.objects. As a side-effect, this makes these files consistent with configuration files. Change-Id: I11153502b430822130722839e1fa767b82a027aa Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/15981 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Diffstat (limited to 'src/cpu/simple')
-rw-r--r--src/cpu/simple/AtomicSimpleCPU.py4
-rw-r--r--src/cpu/simple/BaseSimpleCPU.py9
-rw-r--r--src/cpu/simple/NonCachingSimpleCPU.py2
-rw-r--r--src/cpu/simple/TimingSimpleCPU.py3
-rw-r--r--src/cpu/simple/probes/SimPoint.py2
5 files changed, 11 insertions, 9 deletions
diff --git a/src/cpu/simple/AtomicSimpleCPU.py b/src/cpu/simple/AtomicSimpleCPU.py
index 15a3feb69..d9dee461b 100644
--- a/src/cpu/simple/AtomicSimpleCPU.py
+++ b/src/cpu/simple/AtomicSimpleCPU.py
@@ -39,8 +39,8 @@
# Authors: Nathan Binkert
from m5.params import *
-from BaseSimpleCPU import BaseSimpleCPU
-from SimPoint import SimPoint
+from m5.objects.BaseSimpleCPU import BaseSimpleCPU
+from m5.objects.SimPoint import SimPoint
class AtomicSimpleCPU(BaseSimpleCPU):
"""Simple CPU model executing a configurable number of
diff --git a/src/cpu/simple/BaseSimpleCPU.py b/src/cpu/simple/BaseSimpleCPU.py
index b40458482..6714295d2 100644
--- a/src/cpu/simple/BaseSimpleCPU.py
+++ b/src/cpu/simple/BaseSimpleCPU.py
@@ -30,9 +30,10 @@ from __future__ import print_function
from m5.defines import buildEnv
from m5.params import *
-from BaseCPU import BaseCPU
-from DummyChecker import DummyChecker
-from BranchPredictor import *
+
+from m5.objects.BaseCPU import BaseCPU
+from m5.objects.DummyChecker import DummyChecker
+from m5.objects.BranchPredictor import *
class BaseSimpleCPU(BaseCPU):
type = 'BaseSimpleCPU'
@@ -41,7 +42,7 @@ class BaseSimpleCPU(BaseCPU):
def addCheckerCpu(self):
if buildEnv['TARGET_ISA'] in ['arm']:
- from ArmTLB import ArmTLB
+ from m5.objects.ArmTLB import ArmTLB
self.checker = DummyChecker(workload = self.workload)
self.checker.itb = ArmTLB(size = self.itb.size)
diff --git a/src/cpu/simple/NonCachingSimpleCPU.py b/src/cpu/simple/NonCachingSimpleCPU.py
index 2905a79ac..3fe0e02c3 100644
--- a/src/cpu/simple/NonCachingSimpleCPU.py
+++ b/src/cpu/simple/NonCachingSimpleCPU.py
@@ -36,7 +36,7 @@
# Authors: Andreas Sandberg
from m5.params import *
-from AtomicSimpleCPU import AtomicSimpleCPU
+from m5.objects.AtomicSimpleCPU import AtomicSimpleCPU
class NonCachingSimpleCPU(AtomicSimpleCPU):
"""Simple CPU model based on the atomic CPU. Unlike the atomic CPU,
diff --git a/src/cpu/simple/TimingSimpleCPU.py b/src/cpu/simple/TimingSimpleCPU.py
index 25149eaa8..134c8bb35 100644
--- a/src/cpu/simple/TimingSimpleCPU.py
+++ b/src/cpu/simple/TimingSimpleCPU.py
@@ -27,7 +27,8 @@
# Authors: Nathan Binkert
from m5.params import *
-from BaseSimpleCPU import BaseSimpleCPU
+
+from m5.objects.BaseSimpleCPU import BaseSimpleCPU
class TimingSimpleCPU(BaseSimpleCPU):
type = 'TimingSimpleCPU'
diff --git a/src/cpu/simple/probes/SimPoint.py b/src/cpu/simple/probes/SimPoint.py
index ac6ec0730..14766a791 100644
--- a/src/cpu/simple/probes/SimPoint.py
+++ b/src/cpu/simple/probes/SimPoint.py
@@ -36,7 +36,7 @@
# Authors: Curtis Dunham
from m5.params import *
-from Probe import ProbeListenerObject
+from m5.objects.Probe import ProbeListenerObject
class SimPoint(ProbeListenerObject):
"""Probe for collecting SimPoint Basic Block Vectors (BBVs)."""