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authorSteve Reinhardt <stever@eecs.umich.edu>2007-06-23 13:26:30 -0700
committerSteve Reinhardt <stever@eecs.umich.edu>2007-06-23 13:26:30 -0700
commit245b0bd9b94bfaaa188b7e945f91c0e4a9909cbe (patch)
tree7ca0de263839f60d35cd6cf0ca8c17d94c375209 /src/cpu/simple_thread.hh
parent57ff2604e59647c6afe988767186f13c80c1aa16 (diff)
parentac19e0c5050219cbb0579a319fa3fab5cf92835d (diff)
downloadgem5-245b0bd9b94bfaaa188b7e945f91c0e4a9909cbe.tar.xz
Merge vm1.(none):/home/stever/bk/newmem-head
into vm1.(none):/home/stever/bk/newmem-cache2 src/base/traceflags.py: Hand merge. --HG-- extra : convert_revision : 9e7539eeab4220ed7a7237457a8f336f79216924
Diffstat (limited to 'src/cpu/simple_thread.hh')
-rw-r--r--src/cpu/simple_thread.hh8
1 files changed, 4 insertions, 4 deletions
diff --git a/src/cpu/simple_thread.hh b/src/cpu/simple_thread.hh
index 95848ee2c..c20fe3d90 100644
--- a/src/cpu/simple_thread.hh
+++ b/src/cpu/simple_thread.hh
@@ -349,22 +349,22 @@ class SimpleThread : public ThreadState
regs.setNextNPC(val);
}
- MiscReg readMiscRegNoEffect(int misc_reg)
+ MiscReg readMiscRegNoEffect(int misc_reg, unsigned tid = 0)
{
return regs.readMiscRegNoEffect(misc_reg);
}
- MiscReg readMiscReg(int misc_reg)
+ MiscReg readMiscReg(int misc_reg, unsigned tid = 0)
{
return regs.readMiscReg(misc_reg, tc);
}
- void setMiscRegNoEffect(int misc_reg, const MiscReg &val)
+ void setMiscRegNoEffect(int misc_reg, const MiscReg &val, unsigned tid = 0)
{
return regs.setMiscRegNoEffect(misc_reg, val);
}
- void setMiscReg(int misc_reg, const MiscReg &val)
+ void setMiscReg(int misc_reg, const MiscReg &val, unsigned tid = 0)
{
return regs.setMiscReg(misc_reg, val, tc);
}