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authorGiacomo Gabrielli <giacomo.gabrielli@arm.com>2018-10-23 13:51:52 +0100
committerGiacomo Gabrielli <giacomo.gabrielli@arm.com>2019-05-11 09:34:27 +0000
commitd0e4cdc9c36466a3dbef8c9f9f509cce8f1a6c34 (patch)
tree231e5efecbf42e376b5175affddb88304f485013 /src/cpu/simple_thread.hh
parentc4bc23453133751a1a5858743e6b1266f735d3dc (diff)
downloadgem5-d0e4cdc9c36466a3dbef8c9f9f509cce8f1a6c34.tar.xz
cpu: Add a memory access predicate
This changeset introduces a new predicate to guard memory accesses. The most immediate use for this is to allow proper handling of predicated-false vector contiguous loads and predicated-false micro-ops of vector gather loads (added in separate changesets). Change-Id: Ice6894fe150faec2f2f7ab796a00c99ac843810a Signed-off-by: Giacomo Gabrielli <giacomo.gabrielli@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/17991 Tested-by: kokoro <noreply+kokoro@google.com> Reviewed-by: Bradley Wang <radwang@ucdavis.edu> Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com> Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>
Diffstat (limited to 'src/cpu/simple_thread.hh')
-rw-r--r--src/cpu/simple_thread.hh15
1 files changed, 15 insertions, 0 deletions
diff --git a/src/cpu/simple_thread.hh b/src/cpu/simple_thread.hh
index 733047f71..8b5e49a3e 100644
--- a/src/cpu/simple_thread.hh
+++ b/src/cpu/simple_thread.hh
@@ -117,6 +117,9 @@ class SimpleThread : public ThreadState, public ThreadContext
/** Did this instruction execute or is it predicated false */
bool predicate;
+ /** True if the memory access should be skipped for this instruction */
+ bool memAccPredicate;
+
public:
std::string name() const
{
@@ -576,6 +579,18 @@ class SimpleThread : public ThreadState, public ThreadContext
unsigned readStCondFailures() const override { return storeCondFailures; }
+ bool
+ readMemAccPredicate()
+ {
+ return memAccPredicate;
+ }
+
+ void
+ setMemAccPredicate(bool val)
+ {
+ memAccPredicate = val;
+ }
+
void
setStCondFailures(unsigned sc_failures) override
{