summaryrefslogtreecommitdiff
path: root/src/cpu/static_inst.hh
diff options
context:
space:
mode:
authorAndreas Sandberg <Andreas.Sandberg@ARM.com>2014-09-03 07:42:22 -0400
committerAndreas Sandberg <Andreas.Sandberg@ARM.com>2014-09-03 07:42:22 -0400
commit326662b01b0fbb7fe4e38cec7a96222d2891808b (patch)
tree35bbca1174a6262d3f69dcf729682e1183f8dede /src/cpu/static_inst.hh
parente1ac9629398027186ef4c2a66772aeff2b4c6792 (diff)
downloadgem5-326662b01b0fbb7fe4e38cec7a96222d2891808b.tar.xz
arch, cpu: Factor out the ExecContext into a proper base class
We currently generate and compile one version of the ISA code per CPU model. This is obviously wasting a lot of resources at compile time. This changeset factors out the interface into a separate ExecContext class, which also serves as documentation for the interface between CPUs and the ISA code. While doing so, this changeset also fixes up interface inconsistencies between the different CPU models. The main argument for using one set of ISA code per CPU model has always been performance as this avoid indirect branches in the generated code. However, this argument does not hold water. Booting Linux on a simulated ARM system running in atomic mode (opt/10.linux-boot/realview-simple-atomic) is actually 2% faster (compiled using clang 3.4) after applying this patch. Additionally, compilation time is decreased by 35%.
Diffstat (limited to 'src/cpu/static_inst.hh')
-rw-r--r--src/cpu/static_inst.hh38
1 files changed, 20 insertions, 18 deletions
diff --git a/src/cpu/static_inst.hh b/src/cpu/static_inst.hh
index 375b7d0ba..c4dd3a6b5 100644
--- a/src/cpu/static_inst.hh
+++ b/src/cpu/static_inst.hh
@@ -50,19 +50,7 @@
// forward declarations
class Packet;
-struct O3CPUImpl;
-template <class Impl> class BaseO3DynInst;
-typedef BaseO3DynInst<O3CPUImpl> O3DynInst;
-class InOrderDynInst;
-
-class CheckerCPU;
-class AtomicSimpleCPU;
-class TimingSimpleCPU;
-class InorderCPU;
-namespace Minor
-{
- class ExecContext;
-};
+class ExecContext;
class SymbolTable;
@@ -267,11 +255,25 @@ class StaticInst : public RefCounted, public StaticInstFlags
public:
virtual ~StaticInst();
-/**
- * The execute() signatures are auto-generated by scons based on the
- * set of CPU models we are compiling in today.
- */
-#include "cpu/static_inst_exec_sigs.hh"
+ virtual Fault execute(ExecContext *xc,
+ Trace::InstRecord *traceData) const = 0;
+ virtual Fault eaComp(ExecContext *xc,
+ Trace::InstRecord *traceData) const
+ {
+ panic("eaComp not defined!");
+ }
+
+ virtual Fault initiateAcc(ExecContext *xc,
+ Trace::InstRecord *traceData) const
+ {
+ panic("initiateAcc not defined!");
+ }
+
+ virtual Fault completeAcc(Packet *pkt, ExecContext *xc,
+ Trace::InstRecord *traceData) const
+ {
+ panic("completeAcc not defined!");
+ }
virtual void advancePC(TheISA::PCState &pcState) const = 0;