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author | Korey Sewell <ksewell@umich.edu> | 2009-02-10 15:49:29 -0800 |
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committer | Korey Sewell <ksewell@umich.edu> | 2009-02-10 15:49:29 -0800 |
commit | 2d0a66cbc123fc345deb070c323130382518f367 (patch) | |
tree | 6f52928b6ffce6fb56c26f543961b12cd9f5d0f4 /src/cpu/static_inst.hh | |
parent | 20c5ec6e1cb52d9e0f39d50bb254bffda139c4ea (diff) | |
download | gem5-2d0a66cbc123fc345deb070c323130382518f367.tar.xz |
CPU: Prepare CPU models for the new in-order CPU model.
Some new functions and forward declarations are necessary to make things work
Diffstat (limited to 'src/cpu/static_inst.hh')
-rw-r--r-- | src/cpu/static_inst.hh | 11 |
1 files changed, 8 insertions, 3 deletions
diff --git a/src/cpu/static_inst.hh b/src/cpu/static_inst.hh index 032a304ad..f28b53ccf 100644 --- a/src/cpu/static_inst.hh +++ b/src/cpu/static_inst.hh @@ -56,9 +56,8 @@ class Packet; class O3CPUImpl; template <class Impl> class BaseO3DynInst; typedef BaseO3DynInst<O3CPUImpl> O3DynInst; - -template <class Impl> -class OzoneDynInst; +template <class Impl> class OzoneDynInst; +class InOrderDynInst; class CheckerCPU; class FastCPU; @@ -434,6 +433,12 @@ class StaticInst : public StaticInstBase */ bool hasBranchTarget(Addr pc, ThreadContext *tc, Addr &tgt) const; + virtual Request::Flags memAccFlags() + { + panic("StaticInst::memAccFlags called on non-memory instruction"); + return 0; + }; + /** * Return string representation of disassembled instruction. * The default version of this function will call the internal |