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| author | Andreas Hansson <andreas.hansson@arm.com> | 2012-10-15 08:12:35 -0400 |
|---|---|---|
| committer | Andreas Hansson <andreas.hansson@arm.com> | 2012-10-15 08:12:35 -0400 |
| commit | 2a740aa09682c32eb8f1f8880f279c943d8c6ee1 (patch) | |
| tree | 61ca1dcb9336bc1f4dbc791c876875c1c260ca8d /src/cpu/testers/memtest | |
| parent | 9baa35ba802f2cfb9fb9ecdebf111f4cd793a428 (diff) | |
| download | gem5-2a740aa09682c32eb8f1f8880f279c943d8c6ee1.tar.xz | |
Port: Add protocol-agnostic ports in the port hierarchy
This patch adds an additional level of ports in the inheritance
hierarchy, separating out the protocol-specific and protocl-agnostic
parts. All the functionality related to the binding of ports is now
confined to use BaseMaster/BaseSlavePorts, and all the
protocol-specific parts stay in the Master/SlavePort. In the future it
will be possible to add other protocol-specific implementations.
The functions used in the binding of ports, i.e. getMaster/SlavePort
now use the base classes, and the index parameter is updated to use
the PortID typedef with the symbolic InvalidPortID as the default.
Diffstat (limited to 'src/cpu/testers/memtest')
| -rw-r--r-- | src/cpu/testers/memtest/memtest.cc | 4 | ||||
| -rw-r--r-- | src/cpu/testers/memtest/memtest.hh | 4 |
2 files changed, 4 insertions, 4 deletions
diff --git a/src/cpu/testers/memtest/memtest.cc b/src/cpu/testers/memtest/memtest.cc index 7ea6ad84b..ea3e5fd9b 100644 --- a/src/cpu/testers/memtest/memtest.cc +++ b/src/cpu/testers/memtest/memtest.cc @@ -131,8 +131,8 @@ MemTest::MemTest(const Params *p) dmaOutstanding = false; } -MasterPort & -MemTest::getMasterPort(const std::string &if_name, int idx) +BaseMasterPort & +MemTest::getMasterPort(const std::string &if_name, PortID idx) { if (if_name == "functional") return funcPort; diff --git a/src/cpu/testers/memtest/memtest.hh b/src/cpu/testers/memtest/memtest.hh index 94617c876..cb5f8300f 100644 --- a/src/cpu/testers/memtest/memtest.hh +++ b/src/cpu/testers/memtest/memtest.hh @@ -59,8 +59,8 @@ class MemTest : public MemObject // main simulation loop (one cycle) void tick(); - virtual MasterPort &getMasterPort(const std::string &if_name, - int idx = -1); + virtual BaseMasterPort &getMasterPort(const std::string &if_name, + PortID idx = InvalidPortID); /** * Print state of address in memory system via PrintReq (for |