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authorKorey Sewell <ksewell@umich.edu>2007-11-13 16:58:16 -0500
committerKorey Sewell <ksewell@umich.edu>2007-11-13 16:58:16 -0500
commit269259004943b80916ec9b6354f2fc00c811c88b (patch)
tree4a01b0300aef6692a787f85d42280a1dbdb086e6 /src/cpu/thread_context.hh
parent422ab8bec0034a6b703578ec2c92350c6382875a (diff)
downloadgem5-269259004943b80916ec9b6354f2fc00c811c88b.tar.xz
Add in files from merge-bare-iron, get them compiling in FS and SE mode
--HG-- extra : convert_revision : d4e19afda897bc3797868b40469ce2ec7ec7d251
Diffstat (limited to 'src/cpu/thread_context.hh')
-rw-r--r--src/cpu/thread_context.hh6
1 files changed, 6 insertions, 0 deletions
diff --git a/src/cpu/thread_context.hh b/src/cpu/thread_context.hh
index 31fdb42c2..fd35efc91 100644
--- a/src/cpu/thread_context.hh
+++ b/src/cpu/thread_context.hh
@@ -238,6 +238,8 @@ class ThreadContext
virtual void setRegOtherThread(int misc_reg, const MiscReg &val, unsigned tid) { };
+ virtual void setShadowSet(int css) = 0;
+
// Also not necessarily the best location for these two. Hopefully will go
// away once we decide upon where st cond failures goes.
virtual unsigned readStCondFailures() = 0;
@@ -407,6 +409,10 @@ class ProxyThreadContext : public ThreadContext
void setFloatRegBits(int reg_idx, FloatRegBits val)
{ actualTC->setFloatRegBits(reg_idx, val); }
+ void setShadowSet(int css){
+ return actualTC->setShadowSet(css);
+ }
+
uint64_t readPC() { return actualTC->readPC(); }
void setPC(uint64_t val) { actualTC->setPC(val); }