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| author | Korey Sewell <ksewell@umich.edu> | 2007-06-22 19:03:42 -0400 |
|---|---|---|
| committer | Korey Sewell <ksewell@umich.edu> | 2007-06-22 19:03:42 -0400 |
| commit | 753adb38d5471d23315d1bcfc6a744d1c6e03975 (patch) | |
| tree | 9ae1cc842f4c3756acf86147a5fd6772d7a6622f /src/cpu/thread_context.hh | |
| parent | 16c1b5484f576b6aebea9ab5ffab4ea64f080de0 (diff) | |
| download | gem5-753adb38d5471d23315d1bcfc6a744d1c6e03975.tar.xz | |
mips import pt. 1
src/arch/mips/SConscript:
"mips import pt.1".
--HG--
extra : convert_revision : 2e393341938bebf32fb638a209262d074fad4cc1
Diffstat (limited to 'src/cpu/thread_context.hh')
| -rw-r--r-- | src/cpu/thread_context.hh | 4 |
1 files changed, 4 insertions, 0 deletions
diff --git a/src/cpu/thread_context.hh b/src/cpu/thread_context.hh index 05c409c95..3706d8543 100644 --- a/src/cpu/thread_context.hh +++ b/src/cpu/thread_context.hh @@ -234,6 +234,10 @@ class ThreadContext virtual void setMiscReg(int misc_reg, const MiscReg &val) = 0; + virtual uint64_t readRegOtherThread(int misc_reg, unsigned tid) { return 0; } + + virtual void setRegOtherThread(int misc_reg, const MiscReg &val, unsigned tid) { }; + // Also not necessarily the best location for these two. Hopefully will go // away once we decide upon where st cond failures goes. virtual unsigned readStCondFailures() = 0; |