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authorGabe Black <gblack@eecs.umich.edu>2012-01-31 22:40:08 -0800
committerGabe Black <gblack@eecs.umich.edu>2012-01-31 22:40:08 -0800
commitea8b347dc5d375572d8d19770024ec8be5fd5017 (patch)
tree56bb75b1f071a749b7e90218d0d6b0e9265657bb /src/cpu/thread_context.hh
parente88165a431a90cf7e33e205794caed898ca6fcb1 (diff)
parent7d4f18770073d968c70cd3ffcdd117f50a6056a2 (diff)
downloadgem5-ea8b347dc5d375572d8d19770024ec8be5fd5017.tar.xz
Merge with head, hopefully the last time for this batch.
Diffstat (limited to 'src/cpu/thread_context.hh')
-rw-r--r--src/cpu/thread_context.hh29
1 files changed, 29 insertions, 0 deletions
diff --git a/src/cpu/thread_context.hh b/src/cpu/thread_context.hh
index 261ace7cf..2f2e5b02b 100644
--- a/src/cpu/thread_context.hh
+++ b/src/cpu/thread_context.hh
@@ -1,4 +1,16 @@
/*
+ * Copyright (c) 2011 ARM Limited
+ * All rights reserved
+ *
+ * The license below extends only to copyright in the software and shall
+ * not be construed as granting a license to any other intellectual
+ * property including but not limited to intellectual property relating
+ * to a hardware implementation of the functionality of the software
+ * licensed hereunder. You may use the software subject to the license
+ * terms below provided that you ensure that this notice is replicated
+ * unmodified and in its entirety in all distributions of the software,
+ * modified or unmodified, in source code or in binary form.
+ *
* Copyright (c) 2006 The Regents of The University of Michigan
* All rights reserved.
*
@@ -38,6 +50,7 @@
#include "arch/types.hh"
#include "base/types.hh"
#include "config/the_isa.hh"
+#include "config/use_checker.hh"
// @todo: Figure out a more architecture independent way to obtain the ITB and
// DTB pointers.
@@ -120,6 +133,10 @@ class ThreadContext
virtual TheISA::TLB *getDTBPtr() = 0;
+#if USE_CHECKER
+ virtual BaseCPU *getCheckerCpuPtr() = 0;
+#endif
+
virtual Decoder *getDecoderPtr() = 0;
virtual System *getSystemPtr() = 0;
@@ -198,6 +215,10 @@ class ThreadContext
virtual void pcState(const TheISA::PCState &val) = 0;
+#if USE_CHECKER
+ virtual void pcStateNoRecord(const TheISA::PCState &val) = 0;
+#endif
+
virtual Addr instAddr() = 0;
virtual Addr nextInstAddr() = 0;
@@ -287,6 +308,10 @@ class ProxyThreadContext : public ThreadContext
TheISA::TLB *getDTBPtr() { return actualTC->getDTBPtr(); }
+#if USE_CHECKER
+ BaseCPU *getCheckerCpuPtr() { return actualTC->getCheckerCpuPtr(); }
+#endif
+
Decoder *getDecoderPtr() { return actualTC->getDecoderPtr(); }
System *getSystemPtr() { return actualTC->getSystemPtr(); }
@@ -367,6 +392,10 @@ class ProxyThreadContext : public ThreadContext
void pcState(const TheISA::PCState &val) { actualTC->pcState(val); }
+#if USE_CHECKER
+ void pcStateNoRecord(const TheISA::PCState &val) { actualTC->pcState(val); }
+#endif
+
Addr instAddr() { return actualTC->instAddr(); }
Addr nextInstAddr() { return actualTC->nextInstAddr(); }
MicroPC microPC() { return actualTC->microPC(); }