diff options
| author | Nathanael Premillieu <nathanael.premillieu@arm.com> | 2017-04-05 12:46:06 -0500 |
|---|---|---|
| committer | Andreas Sandberg <andreas.sandberg@arm.com> | 2017-07-05 14:43:49 +0000 |
| commit | 5e8287d2e2eaf058495442ea9e32fafc343a0b53 (patch) | |
| tree | 7d0891b8984926f8e404d6ca8247f45695f9fc9b /src/cpu/timing_expr.cc | |
| parent | 864f87f9c56a66dceeca0f4e9470fbaa3001b627 (diff) | |
| download | gem5-5e8287d2e2eaf058495442ea9e32fafc343a0b53.tar.xz | |
arch, cpu: Architectural Register structural indexing
Replace the unified register mapping with a structure associating
a class and an index. It is now much easier to know which class of
register the index is referring to. Also, when adding a new class
there is no need to modify existing ones.
Change-Id: I55b3ac80763702aa2cd3ed2cbff0a75ef7620373
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
[ Fix RISCV build issues ]
Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/2700
Diffstat (limited to 'src/cpu/timing_expr.cc')
| -rw-r--r-- | src/cpu/timing_expr.cc | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/src/cpu/timing_expr.cc b/src/cpu/timing_expr.cc index 88bc5476f..99b4eb6aa 100644 --- a/src/cpu/timing_expr.cc +++ b/src/cpu/timing_expr.cc @@ -58,7 +58,7 @@ TimingExprEvalContext::TimingExprEvalContext(const StaticInstPtr &inst_, uint64_t TimingExprSrcReg::eval(TimingExprEvalContext &context) { - return context.inst->srcRegIdx(index); + return context.inst->srcRegIdx(index).regIdx; } uint64_t TimingExprReadIntReg::eval(TimingExprEvalContext &context) |