summaryrefslogtreecommitdiff
path: root/src/cpu/trace
diff options
context:
space:
mode:
authorAli Saidi <saidi@eecs.umich.edu>2007-09-28 13:21:52 -0400
committerAli Saidi <saidi@eecs.umich.edu>2007-09-28 13:21:52 -0400
commitd325f49b70e52044fd1072afed27227ecd4b2a60 (patch)
tree9157db931a027b3fd5d14330701b7cbf19f58483 /src/cpu/trace
parent887cd6a273f8777580fc3a046090c6b5244e9cad (diff)
downloadgem5-d325f49b70e52044fd1072afed27227ecd4b2a60.tar.xz
Rename cycles() function to ticks()
--HG-- extra : convert_revision : 790eddb793d4f5ba35813d001037bd8601bd76a5
Diffstat (limited to 'src/cpu/trace')
-rw-r--r--src/cpu/trace/trace_cpu.cc4
-rw-r--r--src/cpu/trace/trace_cpu.hh2
2 files changed, 3 insertions, 3 deletions
diff --git a/src/cpu/trace/trace_cpu.cc b/src/cpu/trace/trace_cpu.cc
index e5739b2ce..d3cf34e9d 100644
--- a/src/cpu/trace/trace_cpu.cc
+++ b/src/cpu/trace/trace_cpu.cc
@@ -110,10 +110,10 @@ TraceCPU::tick()
if (mainEventQueue.empty()) {
exitSimLoop("end of memory trace reached");
} else {
- tickEvent.schedule(mainEventQueue.nextEventTime() + cycles(1));
+ tickEvent.schedule(mainEventQueue.nextEventTime() + ticks(1));
}
} else {
- tickEvent.schedule(max(curTick + cycles(1), nextCycle));
+ tickEvent.schedule(max(curTick + ticks(1), nextCycle));
}
}
diff --git a/src/cpu/trace/trace_cpu.hh b/src/cpu/trace/trace_cpu.hh
index 9c96d71d5..b88c7072e 100644
--- a/src/cpu/trace/trace_cpu.hh
+++ b/src/cpu/trace/trace_cpu.hh
@@ -107,7 +107,7 @@ class TraceCPU : public SimObject
MemInterface *dcache_interface,
MemTraceReader *data_trace);
- inline Tick cycles(int numCycles) { return numCycles; }
+ inline Tick ticks(int numCycles) { return numCycles; }
/**
* Perform all the accesses for one cycle.