cpu: Make get(Data|Inst)Port return a Port and not a MasterPort.

No caller uses any of the MasterPort specific properties of these
function's return values, so we can instead return a reference to the
base Port class. This makes it possible for the data and inst ports
to be of any port type, not just gem5 style MasterPorts. This makes
life simpler for, for example, systemc based CPUs which might have TLM
ports.

It also makes it possible for any two CPUs which have compatible ports
to be switched between, as long as the ports they use support being
unbound. Unfortunately that does not include TLM or systemc ports which
are bound permanently.

Change-Id: I98fce5a16d2ef1af051238e929dd96d57a4ac838
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/20240
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Gabe Black <gabeblack@google.com>

1 files changed, 2 insertions, 2 deletions

diff --git a/src/cpu/trace/trace_cpu.hh b/src/cpu/trace/trace_cpu.hh
index c873a349f..ebc14ca81 100644
--- a/src/cpu/trace/trace_cpu.hh
+++ b/src/cpu/trace/trace_cpu.hh
@@ -1146,10 +1146,10 @@ class TraceCPU : public BaseCPU
   public:
 
     /** Used to get a reference to the icache port. */
-    MasterPort &getInstPort() { return icachePort; }
+    Port &getInstPort() { return icachePort; }
 
     /** Used to get a reference to the dcache port. */
-    MasterPort &getDataPort() { return dcachePort; }
+    Port &getDataPort() { return dcachePort; }
 
     void regStats();
 };