Merge zizzer.eecs.umich.edu:/bk/newmem

into  ewok.(none):/home/gblack/m5/newmemo3

src/sim/byteswap.hh:
    Hand Merge

--HG--
extra : convert_revision : 640d33ad0c416934e8a5107768e7f1dce6709ca8

7 files changed, 62 insertions, 25 deletions

diff --git a/src/cpu/base.cc b/src/cpu/base.cc
index 31604ad58..b03bc19a5 100644
--- a/src/cpu/base.cc
+++ b/src/cpu/base.cc
@@ -363,6 +363,12 @@ BaseCPU::ProfileEvent::process()
 }
 
 void
+BaseCPU::post_interrupt(int int_type)
+{
+    interrupts.post(int_type);
+}
+
+void
 BaseCPU::post_interrupt(int int_num, int index)
 {
     checkInterrupts = true;
diff --git a/src/cpu/base.hh b/src/cpu/base.hh
index 8c6b079da..89c7d9dda 100644
--- a/src/cpu/base.hh
+++ b/src/cpu/base.hh
@@ -102,6 +102,7 @@ class BaseCPU : public MemObject
     TheISA::Interrupts interrupts;
 
   public:
+    virtual void post_interrupt(int int_type);
     virtual void post_interrupt(int int_num, int index);
     virtual void clear_interrupt(int int_num, int index);
     virtual void clear_interrupts();
diff --git a/src/cpu/cpuevent.hh b/src/cpu/cpuevent.hh
index 3339f8252..c973621c0 100644
--- a/src/cpu/cpuevent.hh
+++ b/src/cpu/cpuevent.hh
@@ -36,12 +36,14 @@
 
 class ThreadContext;
 
-/** This class creates a global list of events that need a pointer to a
- * thread context. When a switchover takes place the events can be migrated
- * to the new thread context, otherwise you could have a wake timer interrupt
- * go off on a switched out cpu or other unfortunate events. This object MUST be
- * dynamically allocated to avoid it being deleted after a cpu switch happens.
- * */
+/**
+ * This class creates a global list of events that need a pointer to a
+ * thread context. When a switchover takes place the events can be
+ * migrated to the new thread context, otherwise you could have a wake
+ * timer interrupt go off on a switched out cpu or other unfortunate
+ * events. This object MUST be dynamically allocated to avoid it being
+ * deleted after a cpu switch happens.
+ */
 class CpuEvent : public Event
 {
   protected:
@@ -78,8 +80,8 @@ class CpuEventWrapper : public CpuEvent
     T *object;
 
   public:
-    CpuEventWrapper(T *obj, ThreadContext *_tc, EventQueue *q = &mainEventQueue,
-            Priority p = Default_Pri)
+    CpuEventWrapper(T *obj, ThreadContext *_tc,
+        EventQueue *q = &mainEventQueue, Priority p = Default_Pri)
         : CpuEvent(q, _tc, p), object(obj)
     { }
     void process() { (object->*F)(tc); }
diff --git a/src/cpu/exetrace.cc b/src/cpu/exetrace.cc
index 378fcd09b..7ebbf455a 100644
--- a/src/cpu/exetrace.cc
+++ b/src/cpu/exetrace.cc
@@ -59,6 +59,7 @@ using namespace TheISA;
 
 #if THE_ISA == SPARC_ISA && FULL_SYSTEM
 static int diffcount = 0;
+static bool wasMicro = false;
 #endif
 
 namespace Trace {
@@ -124,6 +125,7 @@ inline void printLevelHeader(ostream & os, int level)
 void
 Trace::InstRecord::dump(ostream &outs)
 {
+    DPRINTF(Sparc, "Instruction: %#X\n", staticInst->machInst);
     if (flags[PRINT_REG_DELTA])
     {
 #if THE_ISA == SPARC_ISA
@@ -317,6 +319,24 @@ Trace::InstRecord::dump(ostream &outs)
         bool diffTlb = false;
         Addr m5Pc, lgnPc;
 
+        // We took a trap on a micro-op...
+        if (wasMicro && !staticInst->isMicroOp())
+        {
+            // let's skip comparing this cycle
+            while (!compared)
+                if (shared_data->flags == OWN_M5) {
+                    shared_data->flags = OWN_LEGION;
+                    compared = true;
+                }
+            compared = false;
+            wasMicro = false;
+        }
+
+        if (staticInst->isLastMicroOp())
+            wasMicro = false;
+        else if (staticInst->isMicroOp())
+            wasMicro = true;
+
 
         if(!staticInst->isMicroOp() || staticInst->isLastMicroOp()) {
             while (!compared) {
@@ -607,29 +627,34 @@ Trace::InstRecord::dump(ostream &outs)
                                     << endl;*/
                             }
                         }
-                        printColumnLabels(outs);
-                        char label[8];
-                        for (int x = 0; x < 64; x++) {
-                            if (shared_data->itb[x] !=  ULL(0xFFFFFFFFFFFFFFFF) ||
-                                thread->getITBPtr()->TteRead(x) != ULL(0xFFFFFFFFFFFFFFFF))  {
-                                    sprintf(label, "I-TLB:%02d", x);
-                                    printRegPair(outs, label, thread->getITBPtr()->TteRead(x), shared_data->itb[x]);
+                        if (diffTlb) {
+                            printColumnLabels(outs);
+                            char label[8];
+                            for (int x = 0; x < 64; x++) {
+                                if (shared_data->itb[x] !=  ULL(0xFFFFFFFFFFFFFFFF) ||
+                                    thread->getITBPtr()->TteRead(x) != ULL(0xFFFFFFFFFFFFFFFF))  {
+                                        sprintf(label, "I-TLB:%02d", x);
+                                        printRegPair(outs, label, thread->getITBPtr()->TteRead(x),
+                                                shared_data->itb[x]);
+                                }
                             }
-                        }
-                        for (int x = 0; x < 64; x++) {
-                            if (shared_data->dtb[x] !=  ULL(0xFFFFFFFFFFFFFFFF) ||
-                                thread->getDTBPtr()->TteRead(x) != ULL(0xFFFFFFFFFFFFFFFF))  {
-                                    sprintf(label, "D-TLB:%02d", x);
-                                    printRegPair(outs, label, thread->getDTBPtr()->TteRead(x), shared_data->dtb[x]);
+                            for (int x = 0; x < 64; x++) {
+                                if (shared_data->dtb[x] !=  ULL(0xFFFFFFFFFFFFFFFF) ||
+                                    thread->getDTBPtr()->TteRead(x) != ULL(0xFFFFFFFFFFFFFFFF))  {
+                                        sprintf(label, "D-TLB:%02d", x);
+                                        printRegPair(outs, label, thread->getDTBPtr()->TteRead(x),
+                                                shared_data->dtb[x]);
+                                }
                             }
+                            thread->getITBPtr()->dumpAll();
+                            thread->getDTBPtr()->dumpAll();
                         }
-                        thread->getITBPtr()->dumpAll();
-                        thread->getDTBPtr()->dumpAll();
 
                         diffcount++;
                         if (diffcount > 2)
                             fatal("Differences found between Legion and M5\n");
-                    }
+                    } else
+                        diffcount = 0;
 
                     compared = true;
                     shared_data->flags = OWN_LEGION;
diff --git a/src/cpu/simple/atomic.cc b/src/cpu/simple/atomic.cc
index 8db864153..3b3536e44 100644
--- a/src/cpu/simple/atomic.cc
+++ b/src/cpu/simple/atomic.cc
@@ -497,7 +497,7 @@ AtomicSimpleCPU::tick()
 
             // @todo remove me after debugging with legion done
             if (curStaticInst && (!curStaticInst->isMicroOp() ||
-                        curStaticInst->isLastMicroOp()))
+                        curStaticInst->isFirstMicroOp()))
                 instCnt++;
 
             if (simulate_stalls) {
diff --git a/src/cpu/simple/base.cc b/src/cpu/simple/base.cc
index 4e5754bbb..ddccc5a9b 100644
--- a/src/cpu/simple/base.cc
+++ b/src/cpu/simple/base.cc
@@ -437,6 +437,7 @@ void
 BaseSimpleCPU::advancePC(Fault fault)
 {
     if (fault != NoFault) {
+        curMacroStaticInst = StaticInst::nullStaticInstPtr;
         fault->invoke(tc);
     } else {
         //If we're at the last micro op for this instruction
diff --git a/src/cpu/static_inst.hh b/src/cpu/static_inst.hh
index 523cfae40..5928eea76 100644
--- a/src/cpu/static_inst.hh
+++ b/src/cpu/static_inst.hh
@@ -146,6 +146,7 @@ class StaticInstBase : public RefCounted
         IsMicroOp,	///< Is a microop
         IsDelayedCommit,	///< This microop doesn't commit right away
         IsLastMicroOp,	///< This microop ends a microop sequence
+        IsFirstMicroOp,	///< This microop begins a microop sequence
         //This flag doesn't do anything yet
         IsMicroBranch,	///< This microop branches within the microcode for a macroop
 
@@ -244,6 +245,7 @@ class StaticInstBase : public RefCounted
     bool isMicroOp() const { return flags[IsMicroOp]; }
     bool isDelayedCommit() const { return flags[IsDelayedCommit]; }
     bool isLastMicroOp() const { return flags[IsLastMicroOp]; }
+    bool isFirstMicroOp() const { return flags[IsFirstMicroOp]; }
     //This flag doesn't do anything yet
     bool isMicroBranch() const { return flags[IsMicroBranch]; }
     //@}