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authorFaissal Sleiman <sleimanf@umich.edu>2014-04-19 09:00:30 -0500
committerFaissal Sleiman <sleimanf@umich.edu>2014-04-19 09:00:30 -0500
commita1570f544f7eb24d87a664038705ae6801862eab (patch)
tree653b636176ab47b13c6b4f87f21f457363f62c3e /src/cpu
parentd9fa950396e8f331bbfb1023348c8c680967b1be (diff)
downloadgem5-a1570f544f7eb24d87a664038705ae6801862eab.tar.xz
o3: Fix occupancy checks for SMT
A number of calls to isEmpty() and numFreeEntries() should be thread-specific. In cpu.cc, the fact that tid is /*commented*/ out is a bug. Say the rob has instructions from thread 0 (isEmpty() returns false), and none from thread 1. If we are trying to squash all of thread 1, then readTailInst(thread 1) will be called because rob->isEmpty() returns false. The result is end_it is not in the list and the while statement loops indefinitely back over the cpu's instList. In iew_impl.hh, all threads are told they have the entire remaining IQ, when each thread actually has a certain allocation. The result is extra stalls at the iew dispatch stage which the rename stage usually takes care of. In commit_impl.hh, rob->readHeadInst(thread 1) can be called if the rob only contains instructions from thread 0. This returns a dummyInst (which may work since we are trying to squash all instructions, but hardly seems like the right way to do it). In rob_impl.hh this fix skips the rest of the function more frequently and is more efficient. Committed by: Nilay Vaish <nilay@cs.wisc.edu>
Diffstat (limited to 'src/cpu')
-rw-r--r--src/cpu/o3/commit_impl.hh2
-rw-r--r--src/cpu/o3/cpu.cc2
-rw-r--r--src/cpu/o3/iew_impl.hh2
-rw-r--r--src/cpu/o3/rob_impl.hh2
4 files changed, 4 insertions, 4 deletions
diff --git a/src/cpu/o3/commit_impl.hh b/src/cpu/o3/commit_impl.hh
index 91e8e7681..5ca15f611 100644
--- a/src/cpu/o3/commit_impl.hh
+++ b/src/cpu/o3/commit_impl.hh
@@ -561,7 +561,7 @@ DefaultCommit<Impl>::squashAll(ThreadID tid)
// then use one older sequence number.
// Hopefully this doesn't mess things up. Basically I want to squash
// all instructions of this thread.
- InstSeqNum squashed_inst = rob->isEmpty() ?
+ InstSeqNum squashed_inst = rob->isEmpty(tid) ?
lastCommitedSeqNum[tid] : rob->readHeadInst(tid)->seqNum - 1;
// All younger instructions will be squashed. Set the sequence
diff --git a/src/cpu/o3/cpu.cc b/src/cpu/o3/cpu.cc
index 710482d3c..f87e6a923 100644
--- a/src/cpu/o3/cpu.cc
+++ b/src/cpu/o3/cpu.cc
@@ -1640,7 +1640,7 @@ FullO3CPU<Impl>::removeInstsNotInROB(ThreadID tid)
if (instList.empty()) {
return;
- } else if (rob.isEmpty(/*tid*/)) {
+ } else if (rob.isEmpty(tid)) {
DPRINTF(O3CPU, "ROB is empty, squashing all insts.\n");
end_it = instList.begin();
rob_empty = true;
diff --git a/src/cpu/o3/iew_impl.hh b/src/cpu/o3/iew_impl.hh
index 9cfbb3cfc..927a8d5a6 100644
--- a/src/cpu/o3/iew_impl.hh
+++ b/src/cpu/o3/iew_impl.hh
@@ -1598,7 +1598,7 @@ DefaultIEW<Impl>::tick()
toRename->iewInfo[tid].usedIQ = true;
toRename->iewInfo[tid].freeIQEntries =
- instQueue.numFreeEntries();
+ instQueue.numFreeEntries(tid);
toRename->iewInfo[tid].usedLSQ = true;
toRename->iewInfo[tid].freeLSQEntries =
ldstQueue.numFreeEntries(tid);
diff --git a/src/cpu/o3/rob_impl.hh b/src/cpu/o3/rob_impl.hh
index c047981a7..61d6bd11b 100644
--- a/src/cpu/o3/rob_impl.hh
+++ b/src/cpu/o3/rob_impl.hh
@@ -486,7 +486,7 @@ template <class Impl>
void
ROB<Impl>::squash(InstSeqNum squash_num, ThreadID tid)
{
- if (isEmpty()) {
+ if (isEmpty(tid)) {
DPRINTF(ROB, "Does not need to squash due to being empty "
"[sn:%i]\n",
squash_num);