inorder/alpha-isa: create eaComp object visible to StaticInst through ISA

Remove subinstructions eaComp/memAcc since unused in CPU Models. Instead, create eaComp that is visible from StaticInst object. Gives InOrder model capability of generating address without actually initiating access
* * *

3 files changed, 14 insertions, 9 deletions

diff --git a/src/cpu/SConscript b/src/cpu/SConscript
index 344deb9cf..854db9f12 100644
--- a/src/cpu/SConscript
+++ b/src/cpu/SConscript
@@ -49,6 +49,8 @@ execfile(models_db.srcnode().abspath)
 # Template for execute() signature.
 exec_sig_template = '''
 virtual Fault execute(%(type)s *xc, Trace::InstRecord *traceData) const = 0;
+virtual Fault eaComp(%(type)s *xc, Trace::InstRecord *traceData) const
+{ panic("eaComp not defined!"); M5_DUMMY_RETURN };
 virtual Fault initiateAcc(%(type)s *xc, Trace::InstRecord *traceData) const
 { panic("initiateAcc not defined!"); M5_DUMMY_RETURN };
 virtual Fault completeAcc(Packet *pkt, %(type)s *xc,
@@ -59,6 +61,8 @@ virtual int memAccSize(%(type)s *xc)
 '''
 
 mem_ini_sig_template = '''
+virtual Fault eaComp(%(type)s *xc, Trace::InstRecord *traceData) const
+{ panic("eaComp not defined!"); M5_DUMMY_RETURN };
 virtual Fault initiateAcc(%s *xc, Trace::InstRecord *traceData) const { panic("Not defined!"); M5_DUMMY_RETURN };
 '''
 
diff --git a/src/cpu/inorder/inorder_dyn_inst.cc b/src/cpu/inorder/inorder_dyn_inst.cc
index 7fc953da2..b6eac04cb 100644
--- a/src/cpu/inorder/inorder_dyn_inst.cc
+++ b/src/cpu/inorder/inorder_dyn_inst.cc
@@ -226,6 +226,13 @@ InOrderDynInst::execute()
 }
 
 Fault
+InOrderDynInst::calcEA()
+{
+    this->fault = this->staticInst->eaComp(this, this->traceData);
+    return this->fault;
+}
+
+Fault
 InOrderDynInst::initiateAcc()
 {
     // @todo: Pretty convoluted way to avoid squashing from happening
@@ -275,16 +282,9 @@ void InOrderDynInst::deleteStages() {
 }
 
 Fault
-InOrderDynInst::calcEA()
-{
-    return staticInst->eaCompInst()->execute(this, this->traceData);
-}
-
-Fault
 InOrderDynInst::memAccess()
 {
-    //return staticInst->memAccInst()->execute(this, this->traceData);
-    return initiateAcc( );
+    return initiateAcc();
 }
 
 void
diff --git a/src/cpu/inorder/pipeline_traits.cc b/src/cpu/inorder/pipeline_traits.cc
index eb899452a..1c17b0d3f 100644
--- a/src/cpu/inorder/pipeline_traits.cc
+++ b/src/cpu/inorder/pipeline_traits.cc
@@ -99,8 +99,8 @@ bool createBackEndSchedule(DynInstPtr &inst)
     if ( inst->isNonSpeculative() ) {
         // skip execution of non speculative insts until later
     } else if ( inst->isMemRef() ) {
-        E->needs(AGEN, AGENUnit::GenerateAddr);
         if ( inst->isLoad() ) {
+            E->needs(AGEN, AGENUnit::GenerateAddr);
             E->needs(DTLB, TLBUnit::DataLookup);
             E->needs(DCache, CacheUnit::InitiateReadData);
         }
@@ -121,6 +121,7 @@ bool createBackEndSchedule(DynInstPtr &inst)
         M->needs(DCache, CacheUnit::CompleteReadData);
     } else if ( inst->isStore() ) {
         M->needs(RegManager, UseDefUnit::ReadSrcReg, 1);
+        M->needs(AGEN, AGENUnit::GenerateAddr);
         M->needs(DTLB, TLBUnit::DataLookup);
         M->needs(DCache, CacheUnit::InitiateWriteData);
     }