merge

100 files changed, 614 insertions, 142 deletions

diff --git a/src/cpu/BaseCPU.py b/src/cpu/BaseCPU.py
index 4661375ba..ac734e5ac 100644
--- a/src/cpu/BaseCPU.py
+++ b/src/cpu/BaseCPU.py
@@ -26,37 +26,43 @@
 #
 # Authors: Nathan Binkert
 
-from MemObject import MemObject
+import sys
+
+from m5.defines import buildEnv
 from m5.params import *
 from m5.proxy import *
-from m5 import build_env
+
 from Bus import Bus
 from InstTracer import InstTracer
 from ExeTracer import ExeTracer
-import sys
+from MemObject import MemObject
 
 default_tracer = ExeTracer()
 
-if build_env['TARGET_ISA'] == 'alpha':
+if buildEnv['TARGET_ISA'] == 'alpha':
     from AlphaTLB import AlphaDTB, AlphaITB
-    if build_env['FULL_SYSTEM']:
+    if buildEnv['FULL_SYSTEM']:
         from AlphaInterrupts import AlphaInterrupts
-elif build_env['TARGET_ISA'] == 'sparc':
+elif buildEnv['TARGET_ISA'] == 'sparc':
     from SparcTLB import SparcTLB
-    if build_env['FULL_SYSTEM']:
+    if buildEnv['FULL_SYSTEM']:
         from SparcInterrupts import SparcInterrupts
-elif build_env['TARGET_ISA'] == 'x86':
+elif buildEnv['TARGET_ISA'] == 'x86':
     from X86TLB import X86TLB
-    if build_env['FULL_SYSTEM']:
+    if buildEnv['FULL_SYSTEM']:
         from X86LocalApic import X86LocalApic
-elif build_env['TARGET_ISA'] == 'mips':
+elif buildEnv['TARGET_ISA'] == 'mips':
     from MipsTLB import MipsTLB
-    if build_env['FULL_SYSTEM']:
+    if buildEnv['FULL_SYSTEM']:
         from MipsInterrupts import MipsInterrupts
-elif build_env['TARGET_ISA'] == 'arm':
+elif buildEnv['TARGET_ISA'] == 'arm':
     from ArmTLB import ArmTLB
-    if build_env['FULL_SYSTEM']:
+    if buildEnv['FULL_SYSTEM']:
         from ArmInterrupts import ArmInterrupts
+elif buildEnv['TARGET_ISA'] == 'power':
+    from PowerTLB import PowerTLB
+    if buildEnv['FULL_SYSTEM']:
+        from PowerInterrupts import PowerInterrupts
 
 class BaseCPU(MemObject):
     type = 'BaseCPU'
@@ -76,47 +82,54 @@ class BaseCPU(MemObject):
     do_statistics_insts = Param.Bool(True,
         "enable statistics pseudo instructions")
 
-    if build_env['FULL_SYSTEM']:
+    if buildEnv['FULL_SYSTEM']:
         profile = Param.Latency('0ns', "trace the kernel stack")
         do_quiesce = Param.Bool(True, "enable quiesce instructions")
     else:
         workload = VectorParam.Process("processes to run")
 
-    if build_env['TARGET_ISA'] == 'sparc':
+    if buildEnv['TARGET_ISA'] == 'sparc':
         dtb = Param.SparcTLB(SparcTLB(), "Data TLB")
         itb = Param.SparcTLB(SparcTLB(), "Instruction TLB")
-        if build_env['FULL_SYSTEM']:
+        if buildEnv['FULL_SYSTEM']:
             interrupts = Param.SparcInterrupts(
                 SparcInterrupts(), "Interrupt Controller")
-    elif build_env['TARGET_ISA'] == 'alpha':
+    elif buildEnv['TARGET_ISA'] == 'alpha':
         dtb = Param.AlphaTLB(AlphaDTB(), "Data TLB")
         itb = Param.AlphaTLB(AlphaITB(), "Instruction TLB")
-        if build_env['FULL_SYSTEM']:
+        if buildEnv['FULL_SYSTEM']:
             interrupts = Param.AlphaInterrupts(
                 AlphaInterrupts(), "Interrupt Controller")
-    elif build_env['TARGET_ISA'] == 'x86':
+    elif buildEnv['TARGET_ISA'] == 'x86':
         dtb = Param.X86TLB(X86TLB(), "Data TLB")
         itb = Param.X86TLB(X86TLB(), "Instruction TLB")
-        if build_env['FULL_SYSTEM']:
+        if buildEnv['FULL_SYSTEM']:
             _localApic = X86LocalApic(pio_addr=0x2000000000000000)
             interrupts = \
                 Param.X86LocalApic(_localApic, "Interrupt Controller")
-    elif build_env['TARGET_ISA'] == 'mips':
+    elif buildEnv['TARGET_ISA'] == 'mips':
         dtb = Param.MipsTLB(MipsTLB(), "Data TLB")
         itb = Param.MipsTLB(MipsTLB(), "Instruction TLB")
-        if build_env['FULL_SYSTEM']:
+        if buildEnv['FULL_SYSTEM']:
             interrupts = Param.MipsInterrupts(
                     MipsInterrupts(), "Interrupt Controller")
-    elif build_env['TARGET_ISA'] == 'arm':
+    elif buildEnv['TARGET_ISA'] == 'arm':
         UnifiedTLB = Param.Bool(True, "Is this a Unified TLB?")
         dtb = Param.ArmTLB(ArmTLB(), "Data TLB")
         itb = Param.ArmTLB(ArmTLB(), "Instruction TLB")
-        if build_env['FULL_SYSTEM']:
+        if buildEnv['FULL_SYSTEM']:
             interrupts = Param.ArmInterrupts(
                     ArmInterrupts(), "Interrupt Controller")
+    elif buildEnv['TARGET_ISA'] == 'power':
+        UnifiedTLB = Param.Bool(True, "Is this a Unified TLB?")
+        dtb = Param.PowerTLB(PowerTLB(), "Data TLB")
+        itb = Param.PowerTLB(PowerTLB(), "Instruction TLB")
+        if buildEnv['FULL_SYSTEM']:
+            interrupts = Param.PowerInterrupts(
+                    PowerInterrupts(), "Interrupt Controller")
     else:
         print "Don't know what TLB to use for ISA %s" % \
-            build_env['TARGET_ISA']
+            buildEnv['TARGET_ISA']
         sys.exit(1)
 
     max_insts_all_threads = Param.Counter(0,
@@ -139,7 +152,7 @@ class BaseCPU(MemObject):
     tracer = Param.InstTracer(default_tracer, "Instruction tracer")
 
     _mem_ports = []
-    if build_env['TARGET_ISA'] == 'x86' and build_env['FULL_SYSTEM']:
+    if buildEnv['TARGET_ISA'] == 'x86' and buildEnv['FULL_SYSTEM']:
         _mem_ports = ["itb.walker.port",
                       "dtb.walker.port",
                       "interrupts.pio",
@@ -157,7 +170,7 @@ class BaseCPU(MemObject):
         self.icache_port = ic.cpu_side
         self.dcache_port = dc.cpu_side
         self._mem_ports = ['icache.mem_side', 'dcache.mem_side']
-        if build_env['TARGET_ISA'] == 'x86' and build_env['FULL_SYSTEM']:
+        if buildEnv['TARGET_ISA'] == 'x86' and buildEnv['FULL_SYSTEM']:
             self._mem_ports += ["itb.walker_port", "dtb.walker_port"]
 
     def addTwoLevelCacheHierarchy(self, ic, dc, l2c):
@@ -168,7 +181,7 @@ class BaseCPU(MemObject):
         self.l2cache.cpu_side = self.toL2Bus.port
         self._mem_ports = ['l2cache.mem_side']
 
-    if build_env['TARGET_ISA'] == 'mips':
+    if buildEnv['TARGET_ISA'] == 'mips':
         CP0_IntCtl_IPTI = Param.Unsigned(0,"No Description")
         CP0_IntCtl_IPPCI = Param.Unsigned(0,"No Description")
         CP0_SrsCtl_HSS = Param.Unsigned(0,"No Description")
diff --git a/src/cpu/CheckerCPU.py b/src/cpu/CheckerCPU.py
index bff9af62d..132254413 100644
--- a/src/cpu/CheckerCPU.py
+++ b/src/cpu/CheckerCPU.py
@@ -27,7 +27,6 @@
 # Authors: Nathan Binkert
 
 from m5.params import *
-from m5 import build_env
 from BaseCPU import BaseCPU
 
 class CheckerCPU(BaseCPU):
diff --git a/src/cpu/SConscript b/src/cpu/SConscript
index ea79b622c..b89a589c6 100644
--- a/src/cpu/SConscript
+++ b/src/cpu/SConscript
@@ -160,6 +160,7 @@ TraceFlag('DynInst')
 TraceFlag('ExecEnable')
 TraceFlag('ExecCPSeq')
 TraceFlag('ExecEffAddr')
+TraceFlag('ExecFaulting', 'Trace faulting instructions')
 TraceFlag('ExecFetchSeq')
 TraceFlag('ExecOpClass')
 TraceFlag('ExecRegDelta')
@@ -176,6 +177,6 @@ TraceFlag('PCEvent')
 TraceFlag('Quiesce')
 
 CompoundFlag('Exec', [ 'ExecEnable', 'ExecTicks', 'ExecOpClass', 'ExecThread',
-    'ExecEffAddr', 'ExecResult', 'ExecSymbol', 'ExecMicro' ])
+    'ExecEffAddr', 'ExecResult', 'ExecSymbol', 'ExecMicro', 'ExecFaulting' ])
 CompoundFlag('ExecNoTicks', [ 'ExecEnable', 'ExecOpClass', 'ExecThread',
-    'ExecEffAddr', 'ExecResult', 'ExecMicro' ])
+    'ExecEffAddr', 'ExecResult', 'ExecMicro', 'ExecFaulting' ])
diff --git a/src/cpu/base.cc b/src/cpu/base.cc
index e4cb79344..556e7ec6f 100644
--- a/src/cpu/base.cc
+++ b/src/cpu/base.cc
@@ -151,7 +151,7 @@ BaseCPU::BaseCPU(Params *p)
         *counter = numThreads;
         for (ThreadID tid = 0; tid < numThreads; ++tid) {
             Event *event = new CountedExitEvent(cause, *counter);
-            comInstEventQueue[tid]->schedule(event, p->max_insts_any_thread);
+            comInstEventQueue[tid]->schedule(event, p->max_insts_all_threads);
         }
     }
 
diff --git a/src/cpu/base.hh b/src/cpu/base.hh
index 441d9b5dd..bfeec0870 100644
--- a/src/cpu/base.hh
+++ b/src/cpu/base.hh
@@ -38,6 +38,7 @@
 #include "arch/microcode_rom.hh"
 #include "base/statistics.hh"
 #include "config/full_system.hh"
+#include "config/the_isa.hh"
 #include "sim/eventq.hh"
 #include "sim/insttracer.hh"
 #include "mem/mem_object.hh"
diff --git a/src/cpu/base_dyn_inst.hh b/src/cpu/base_dyn_inst.hh
index f4ff88209..31206c81e 100644
--- a/src/cpu/base_dyn_inst.hh
+++ b/src/cpu/base_dyn_inst.hh
@@ -39,6 +39,7 @@
 #include "base/fast_alloc.hh"
 #include "base/trace.hh"
 #include "config/full_system.hh"
+#include "config/the_isa.hh"
 #include "cpu/o3/comm.hh"
 #include "cpu/exetrace.hh"
 #include "cpu/inst_seq.hh"
diff --git a/src/cpu/base_dyn_inst_impl.hh b/src/cpu/base_dyn_inst_impl.hh
index 4ee7d2f2c..70c91ceda 100644
--- a/src/cpu/base_dyn_inst_impl.hh
+++ b/src/cpu/base_dyn_inst_impl.hh
@@ -35,12 +35,11 @@
 
 #include "base/cprintf.hh"
 #include "base/trace.hh"
-
-#include "sim/faults.hh"
+#include "config/the_isa.hh"
+#include "cpu/base_dyn_inst.hh"
 #include "cpu/exetrace.hh"
 #include "mem/request.hh"
-
-#include "cpu/base_dyn_inst.hh"
+#include "sim/faults.hh"
 
 #define NOHASH
 #ifndef NOHASH
diff --git a/src/cpu/checker/cpu.cc b/src/cpu/checker/cpu.cc
index 7dacc58ff..16b779e06 100644
--- a/src/cpu/checker/cpu.cc
+++ b/src/cpu/checker/cpu.cc
@@ -326,7 +326,7 @@ CheckerCPU::checkFlags(Request *req)
 {
     // Remove any dynamic flags that don't have to do with the request itself.
     unsigned flags = unverifiedReq->getFlags();
-    unsigned mask = LOCKED | PHYSICAL | VPTE | ALTMODE | UNCACHEABLE | NO_FAULT;
+    unsigned mask = LOCKED | PHYSICAL | VPTE | ALTMODE | UNCACHEABLE | PREFETCH;
     flags = flags & (mask);
     if (flags == req->getFlags()) {
         return false;
diff --git a/src/cpu/checker/cpu_impl.hh b/src/cpu/checker/cpu_impl.hh
index 26571ed68..81f494630 100644
--- a/src/cpu/checker/cpu_impl.hh
+++ b/src/cpu/checker/cpu_impl.hh
@@ -32,6 +32,7 @@
 #include <string>
 
 #include "base/refcnt.hh"
+#include "config/the_isa.hh"
 #include "cpu/base_dyn_inst.hh"
 #include "cpu/checker/cpu.hh"
 #include "cpu/simple_thread.hh"
diff --git a/src/cpu/checker/thread_context.hh b/src/cpu/checker/thread_context.hh
index d38bd2915..ef7d4c643 100644
--- a/src/cpu/checker/thread_context.hh
+++ b/src/cpu/checker/thread_context.hh
@@ -32,6 +32,7 @@
 #define __CPU_CHECKER_THREAD_CONTEXT_HH__
 
 #include "arch/types.hh"
+#include "config/the_isa.hh"
 #include "cpu/checker/cpu.hh"
 #include "cpu/simple_thread.hh"
 #include "cpu/thread_context.hh"
diff --git a/src/cpu/exetrace.cc b/src/cpu/exetrace.cc
index ea53fb6f5..07be700bb 100644
--- a/src/cpu/exetrace.cc
+++ b/src/cpu/exetrace.cc
@@ -38,6 +38,7 @@
 #include "cpu/exetrace.hh"
 #include "cpu/static_inst.hh"
 #include "cpu/thread_context.hh"
+#include "config/the_isa.hh"
 #include "enums/OpClass.hh"
 
 using namespace std;
diff --git a/src/cpu/inorder/InOrderCPU.py b/src/cpu/inorder/InOrderCPU.py
index 9faadc68c..a0b0466a7 100644
--- a/src/cpu/inorder/InOrderCPU.py
+++ b/src/cpu/inorder/InOrderCPU.py
@@ -28,7 +28,6 @@
 
 from m5.params import *
 from m5.proxy import *
-from m5 import build_env
 from BaseCPU import BaseCPU
 
 class InOrderCPU(BaseCPU):
diff --git a/src/cpu/inorder/SConscript b/src/cpu/inorder/SConscript
index 64f1b5481..82a1028c2 100644
--- a/src/cpu/inorder/SConscript
+++ b/src/cpu/inorder/SConscript
@@ -79,6 +79,7 @@ if 'InOrderCPU' in env['CPU_MODELS']:
 	Source('resources/mult_div_unit.cc')
 	Source('resource_pool.cc')
 	Source('reg_dep_map.cc')
+	Source('thread_state.cc')
 	Source('thread_context.cc')
 	Source('cpu.cc')
 
diff --git a/src/cpu/inorder/cpu.cc b/src/cpu/inorder/cpu.cc
index a2367db63..1e3fdc40e 100644
--- a/src/cpu/inorder/cpu.cc
+++ b/src/cpu/inorder/cpu.cc
@@ -33,24 +33,34 @@
 
 #include "arch/utility.hh"
 #include "config/full_system.hh"
-#include "cpu/exetrace.hh"
+#include "config/the_isa.hh"
 #include "cpu/activity.hh"
-#include "cpu/simple_thread.hh"
-#include "cpu/thread_context.hh"
 #include "cpu/base.hh"
-#include "cpu/inorder/inorder_dyn_inst.hh"
-#include "cpu/inorder/thread_context.hh"
-#include "cpu/inorder/thread_state.hh"
+#include "cpu/exetrace.hh"
 #include "cpu/inorder/cpu.hh"
-#include "params/InOrderCPU.hh"
-#include "cpu/inorder/pipeline_traits.hh"
 #include "cpu/inorder/first_stage.hh"
-#include "cpu/inorder/resources/resource_list.hh"
+#include "cpu/inorder/inorder_dyn_inst.hh"
+#include "cpu/inorder/pipeline_traits.hh"
 #include "cpu/inorder/resource_pool.hh"
+#include "cpu/inorder/resources/resource_list.hh"
+#include "cpu/inorder/thread_context.hh"
+#include "cpu/inorder/thread_state.hh"
+#include "cpu/simple_thread.hh"
+#include "cpu/thread_context.hh"
 #include "mem/translating_port.hh"
+#include "params/InOrderCPU.hh"
 #include "sim/process.hh"
 #include "sim/stat_control.hh"
 
+#if FULL_SYSTEM
+#include "cpu/quiesce_event.hh"
+#include "sim/system.hh"
+#endif
+
+#if THE_ISA == ALPHA_ISA
+#include "arch/alpha/osfpal.hh"
+#endif
+
 using namespace std;
 using namespace TheISA;
 using namespace ThePipeline;
@@ -171,11 +181,16 @@ InOrderCPU::InOrderCPU(Params *params)
       timeBuffer(2 , 2),
       removeInstsThisCycle(false),
       activityRec(params->name, NumStages, 10, params->activity),
+#if FULL_SYSTEM
+      system(params->system),
+      physmem(system->physmem),
+#endif // FULL_SYSTEM
       switchCount(0),
       deferRegistration(false/*params->deferRegistration*/),
       stageTracing(params->stageTracing),
       numVirtProcs(1)
 {
+    ThreadID active_threads;
     cpu_params = params;
 
     resPool = new ResourcePool(this, params);
@@ -183,13 +198,17 @@ InOrderCPU::InOrderCPU(Params *params)
     // Resize for Multithreading CPUs
     thread.resize(numThreads);
 
-    ThreadID active_threads = params->workload.size();
+#if FULL_SYSTEM
+    active_threads = 1;
+#else
+    active_threads = params->workload.size();
 
     if (active_threads > MaxThreads) {
         panic("Workload Size too large. Increase the 'MaxThreads'"
               "in your InOrder implementation or "
               "edit your workload size.");
     }
+#endif
 
     // Bind the fetch & data ports from the resource pool.
     fetchPortIdx = resPool->getPortIdx(params->fetchMemPort);
@@ -203,17 +222,23 @@ InOrderCPU::InOrderCPU(Params *params)
     }
 
     for (ThreadID tid = 0; tid < numThreads; ++tid) {
+#if FULL_SYSTEM
+        // SMT is not supported in FS mode yet.
+        assert(numThreads == 1);
+        thread[tid] = new Thread(this, 0);
+#else
         if (tid < (ThreadID)params->workload.size()) {
             DPRINTF(InOrderCPU, "Workload[%i] process is %#x\n",
-                    tid, this->thread[tid]);
-            this->thread[tid] =
+                    tid, params->workload[tid]->prog_fname);
+            thread[tid] =
                 new Thread(this, tid, params->workload[tid]);
         } else {
             //Allocate Empty thread so M5 can use later
             //when scheduling threads to CPU
             Process* dummy_proc = params->workload[0];
-            this->thread[tid] = new Thread(this, tid, dummy_proc);
+            thread[tid] = new Thread(this, tid, dummy_proc);
         }
+#endif
 
         // Setup the TC that will serve as the interface to the threads/CPU.
         InOrderThreadContext *tc = new InOrderThreadContext;
@@ -410,7 +435,7 @@ InOrderCPU::tick()
             //Tick next_tick = curTick + cycles(1);
             //tickEvent.schedule(next_tick);
             mainEventQueue.schedule(&tickEvent, nextCycle(curTick + 1));
-            DPRINTF(InOrderCPU, "Scheduled CPU for next tick @ %i.\n", nextCycle() + curTick);
+            DPRINTF(InOrderCPU, "Scheduled CPU for next tick @ %i.\n", nextCycle(curTick + 1));
         }
     }
 
@@ -447,13 +472,6 @@ InOrderCPU::init()
 }
 
 void
-InOrderCPU::readFunctional(Addr addr, uint32_t &buffer)
-{
-    tcBase()->getMemPort()->readBlob(addr, (uint8_t*)&buffer, sizeof(uint32_t));
-    buffer = gtoh(buffer);
-}
-
-void
 InOrderCPU::reset()
 {
     for (int i = 0; i < numThreads; i++) {
@@ -468,6 +486,61 @@ InOrderCPU::getPort(const std::string &if_name, int idx)
     return resPool->getPort(if_name, idx);
 }
 
+#if FULL_SYSTEM
+Fault
+InOrderCPU::hwrei(ThreadID tid)
+{
+    panic("hwrei: Unimplemented");
+    
+    return NoFault;
+}
+
+
+bool
+InOrderCPU::simPalCheck(int palFunc, ThreadID tid)
+{
+    panic("simPalCheck: Unimplemented");
+
+    return true;
+}
+
+
+Fault
+InOrderCPU::getInterrupts()
+{
+    // Check if there are any outstanding interrupts
+    return this->interrupts->getInterrupt(this->threadContexts[0]);
+}
+
+
+void
+InOrderCPU::processInterrupts(Fault interrupt)
+{
+    // Check for interrupts here.  For now can copy the code that
+    // exists within isa_fullsys_traits.hh.  Also assume that thread 0
+    // is the one that handles the interrupts.
+    // @todo: Possibly consolidate the interrupt checking code.
+    // @todo: Allow other threads to handle interrupts.
+
+    assert(interrupt != NoFault);
+    this->interrupts->updateIntrInfo(this->threadContexts[0]);
+
+    DPRINTF(InOrderCPU, "Interrupt %s being handled\n", interrupt->name());
+    this->trap(interrupt, 0);
+}
+
+
+void
+InOrderCPU::updateMemPorts()
+{
+    // Update all ThreadContext's memory ports (Functional/Virtual
+    // Ports)
+    ThreadID size = thread.size();
+    for (ThreadID i = 0; i < size; ++i)
+        thread[i]->connectMemPorts(thread[i]->getTC());
+}
+#endif
+
 void
 InOrderCPU::trap(Fault fault, ThreadID tid, int delay)
 {
@@ -1230,6 +1303,22 @@ InOrderCPU::wakeCPU()
     mainEventQueue.schedule(&tickEvent, curTick);
 }
 
+#if FULL_SYSTEM
+
+void
+InOrderCPU::wakeup()
+{
+    if (this->thread[0]->status() != ThreadContext::Suspended)
+        return;
+
+    this->wakeCPU();
+
+    DPRINTF(Quiesce, "Suspended Processor woken\n");
+    this->threadContexts[0]->activate();
+}
+#endif
+
+#if !FULL_SYSTEM
 void
 InOrderCPU::syscall(int64_t callnum, ThreadID tid)
 {
@@ -1251,6 +1340,7 @@ InOrderCPU::syscall(int64_t callnum, ThreadID tid)
     // Clear Non-Speculative Block Variable
     nonSpecInstActive[tid] = false;
 }
+#endif
 
 void
 InOrderCPU::prefetch(DynInstPtr inst)
diff --git a/src/cpu/inorder/cpu.hh b/src/cpu/inorder/cpu.hh
index 75d77c818..3320532ba 100644
--- a/src/cpu/inorder/cpu.hh
+++ b/src/cpu/inorder/cpu.hh
@@ -40,10 +40,12 @@
 
 #include "arch/isa_traits.hh"
 #include "arch/types.hh"
+#include "arch/registers.hh"
 #include "base/statistics.hh"
 #include "base/timebuf.hh"
 #include "base/types.hh"
 #include "config/full_system.hh"
+#include "config/the_isa.hh"
 #include "cpu/activity.hh"
 #include "cpu/base.hh"
 #include "cpu/simple_thread.hh"
@@ -297,6 +299,32 @@ class InOrderCPU : public BaseCPU
     /** Get a Memory Port */
     Port* getPort(const std::string &if_name, int idx = 0);
 
+#if FULL_SYSTEM
+    /** HW return from error interrupt. */
+    Fault hwrei(ThreadID tid);
+
+    bool simPalCheck(int palFunc, ThreadID tid);
+
+    /** Returns the Fault for any valid interrupt. */
+    Fault getInterrupts();
+
+    /** Processes any an interrupt fault. */
+    void processInterrupts(Fault interrupt);
+
+    /** Halts the CPU. */
+    void halt() { panic("Halt not implemented!\n"); }
+
+    /** Update the Virt and Phys ports of all ThreadContexts to
+     * reflect change in memory connections. */
+    void updateMemPorts();
+
+    /** Check if this address is a valid instruction address. */
+    bool validInstAddr(Addr addr) { return true; }
+
+    /** Check if this address is a valid data address. */
+    bool validDataAddr(Addr addr) { return true; }
+#endif
+
     /** trap() - sets up a trap event on the cpuTraps to handle given fault.
      *  trapCPU() - Traps to handle given fault
      */
@@ -578,8 +606,6 @@ class InOrderCPU : public BaseCPU
     ActivityRecorder activityRec;
 
   public:
-    void readFunctional(Addr addr, uint32_t &buffer);
-
     /** Number of Active Threads in the CPU */
     ThreadID numActiveThreads() { return activeThreads.size(); }
 
@@ -597,6 +623,10 @@ class InOrderCPU : public BaseCPU
     /** Wakes the CPU, rescheduling the CPU if it's not already active. */
     void wakeCPU();
 
+#if FULL_SYSTEM
+    virtual void wakeup();
+#endif
+
     /** Gets a free thread id. Use if thread ids change across system. */
     ThreadID getFreeTid();
 
@@ -622,6 +652,14 @@ class InOrderCPU : public BaseCPU
         return total;
     }
 
+#if FULL_SYSTEM
+    /** Pointer to the system. */
+    System *system;
+
+    /** Pointer to physical memory. */
+    PhysicalMemory *physmem;
+#endif
+
     /** The global sequence number counter. */
     InstSeqNum globalSeqNum[ThePipeline::MaxThreads];
 
diff --git a/src/cpu/inorder/inorder_cpu_builder.cc b/src/cpu/inorder/inorder_cpu_builder.cc
index 5ee7b31db..a19137dd8 100644
--- a/src/cpu/inorder/inorder_cpu_builder.cc
+++ b/src/cpu/inorder/inorder_cpu_builder.cc
@@ -42,12 +42,17 @@
 InOrderCPU *
 InOrderCPUParams::create()
 {
+#if FULL_SYSTEM
+    // Full-system only supports a single thread for the moment.
+    ThreadID actual_num_threads = 1;
+#else
     ThreadID actual_num_threads =
         (numThreads >= workload.size()) ? numThreads : workload.size();
 
     if (workload.size() == 0) {
         fatal("Must specify at least one workload!");
     }
+#endif
 
     numThreads = actual_num_threads;
 
diff --git a/src/cpu/inorder/inorder_dyn_inst.cc b/src/cpu/inorder/inorder_dyn_inst.cc
index a6abb28b2..5ab839615 100644
--- a/src/cpu/inorder/inorder_dyn_inst.cc
+++ b/src/cpu/inorder/inorder_dyn_inst.cc
@@ -34,15 +34,14 @@
 #include <string>
 #include <sstream>
 
+#include "arch/faults.hh"
 #include "base/cprintf.hh"
 #include "base/trace.hh"
-
-#include "arch/faults.hh"
+#include "config/the_isa.hh"
 #include "cpu/exetrace.hh"
-#include "mem/request.hh"
-
-#include "cpu/inorder/inorder_dyn_inst.hh"
 #include "cpu/inorder/cpu.hh"
+#include "cpu/inorder/inorder_dyn_inst.hh"
+#include "mem/request.hh"
 
 using namespace std;
 using namespace TheISA;
@@ -297,11 +296,39 @@ InOrderDynInst::memAccess()
     return initiateAcc();
 }
 
+
+#if FULL_SYSTEM
+
+Fault
+InOrderDynInst::hwrei()
+{
+    panic("InOrderDynInst: hwrei: unimplemented\n");    
+    return NoFault;
+}
+
+
+void
+InOrderDynInst::trap(Fault fault)
+{
+    this->cpu->trap(fault, this->threadNumber);
+}
+
+
+bool
+InOrderDynInst::simPalCheck(int palFunc)
+{
+#if THE_ISA != ALPHA_ISA
+    panic("simPalCheck called, but PAL only exists in Alpha!\n");
+#endif
+    return this->cpu->simPalCheck(palFunc, this->threadNumber);
+}
+#else
 void
 InOrderDynInst::syscall(int64_t callnum)
 {
     cpu->syscall(callnum, this->threadNumber);
 }
+#endif
 
 void
 InOrderDynInst::prefetch(Addr addr, unsigned flags)
diff --git a/src/cpu/inorder/inorder_dyn_inst.hh b/src/cpu/inorder/inorder_dyn_inst.hh
index e95a6d039..522b4e8d7 100644
--- a/src/cpu/inorder/inorder_dyn_inst.hh
+++ b/src/cpu/inorder/inorder_dyn_inst.hh
@@ -37,25 +37,31 @@
 #include <list>
 #include <string>
 
-#include "arch/isa_traits.hh"
 #include "arch/faults.hh"
-#include "arch/types.hh"
+#include "arch/isa_traits.hh"
 #include "arch/mt.hh"
+#include "arch/types.hh"
 #include "base/fast_alloc.hh"
 #include "base/trace.hh"
-#include "cpu/inorder/inorder_trace.hh"
+#include "base/types.hh"
 #include "config/full_system.hh"
-#include "cpu/thread_context.hh"
+#include "config/the_isa.hh"
 #include "cpu/exetrace.hh"
+#include "cpu/inorder/inorder_trace.hh"
+#include "cpu/inorder/pipeline_traits.hh"
+#include "cpu/inorder/resource.hh"
+#include "cpu/inorder/thread_state.hh"
 #include "cpu/inst_seq.hh"
 #include "cpu/op_class.hh"
 #include "cpu/static_inst.hh"
-#include "cpu/inorder/thread_state.hh"
-#include "cpu/inorder/resource.hh"
-#include "cpu/inorder/pipeline_traits.hh"
+#include "cpu/thread_context.hh"
 #include "mem/packet.hh"
 #include "sim/system.hh"
 
+#if THE_ISA == ALPHA_ISA
+#include "arch/alpha/ev5.hh"
+#endif
+
 /**
  * @file
  * Defines a dynamic instruction context for a inorder CPU model.
@@ -64,6 +70,7 @@
 // Forward declaration.
 class StaticInstPtr;
 class ResourceRequest;
+class Packet;
 
 class InOrderDynInst : public FastAlloc, public RefCounted
 {
@@ -486,7 +493,16 @@ class InOrderDynInst : public FastAlloc, public RefCounted
     void setCurResSlot(unsigned slot_num) { curResSlot = slot_num; }
 
     /** Calls a syscall. */
+#if FULL_SYSTEM
+    /** Calls hardware return from error interrupt. */
+    Fault hwrei();
+    /** Traps to handle specified fault. */
+    void trap(Fault fault);
+    bool simPalCheck(int palFunc);
+#else
+    /** Calls a syscall. */
     void syscall(int64_t callnum);
+#endif
     void prefetch(Addr addr, unsigned flags);
     void writeHint(Addr addr, int size, unsigned flags);
     Fault copySrcTranslate(Addr src);
diff --git a/src/cpu/inorder/inorder_trace.cc b/src/cpu/inorder/inorder_trace.cc
index f12a1b7a9..90c94a4f5 100644
--- a/src/cpu/inorder/inorder_trace.cc
+++ b/src/cpu/inorder/inorder_trace.cc
@@ -31,6 +31,7 @@
 
 #include <iomanip>
 
+#include "config/the_isa.hh"
 #include "cpu/exetrace.hh"
 #include "cpu/inorder/inorder_trace.hh"
 #include "cpu/static_inst.hh"
diff --git a/src/cpu/inorder/pipeline_stage.cc b/src/cpu/inorder/pipeline_stage.cc
index 46b1cbad0..dc0378bf3 100644
--- a/src/cpu/inorder/pipeline_stage.cc
+++ b/src/cpu/inorder/pipeline_stage.cc
@@ -30,6 +30,7 @@
  */
 
 #include "base/str.hh"
+#include "config/the_isa.hh"
 #include "cpu/inorder/pipeline_stage.hh"
 #include "cpu/inorder/resource_pool.hh"
 #include "cpu/inorder/cpu.hh"
diff --git a/src/cpu/inorder/reg_dep_map.cc b/src/cpu/inorder/reg_dep_map.cc
index a405b1fb9..51782a588 100644
--- a/src/cpu/inorder/reg_dep_map.cc
+++ b/src/cpu/inorder/reg_dep_map.cc
@@ -30,6 +30,7 @@
  */
 
 #include "arch/isa_traits.hh"
+#include "config/the_isa.hh"
 #include "cpu/inorder/pipeline_traits.hh"
 #include "cpu/inorder/reg_dep_map.hh"
 #include "cpu/inorder/inorder_dyn_inst.hh"
diff --git a/src/cpu/inorder/reg_dep_map.hh b/src/cpu/inorder/reg_dep_map.hh
index ba2a8c8a3..b78e211bb 100644
--- a/src/cpu/inorder/reg_dep_map.hh
+++ b/src/cpu/inorder/reg_dep_map.hh
@@ -36,6 +36,7 @@
 #include <vector>
 
 #include "arch/isa_traits.hh"
+#include "config/the_isa.hh"
 #include "cpu/inorder/pipeline_traits.hh"
 
 class InOrderCPU;
diff --git a/src/cpu/inorder/resource.hh b/src/cpu/inorder/resource.hh
index 7935e5517..605b7f690 100644
--- a/src/cpu/inorder/resource.hh
+++ b/src/cpu/inorder/resource.hh
@@ -36,6 +36,7 @@
 #include <list>
 #include <string>
 
+#include "base/types.hh"
 #include "cpu/inst_seq.hh"
 #include "cpu/inorder/inorder_dyn_inst.hh"
 #include "cpu/inorder/pipeline_traits.hh"
diff --git a/src/cpu/inorder/resources/bpred_unit.cc b/src/cpu/inorder/resources/bpred_unit.cc
index 2ed8586aa..0e8526fa1 100644
--- a/src/cpu/inorder/resources/bpred_unit.cc
+++ b/src/cpu/inorder/resources/bpred_unit.cc
@@ -33,6 +33,7 @@
 
 #include "base/trace.hh"
 #include "base/traceflags.hh"
+#include "config/the_isa.hh"
 #include "cpu/inorder/resources/bpred_unit.hh"
 
 using namespace std;
diff --git a/src/cpu/inorder/resources/branch_predictor.cc b/src/cpu/inorder/resources/branch_predictor.cc
index 905de0794..ecac5fff0 100644
--- a/src/cpu/inorder/resources/branch_predictor.cc
+++ b/src/cpu/inorder/resources/branch_predictor.cc
@@ -29,6 +29,7 @@
  *
  */
 
+#include "config/the_isa.hh"
 #include "cpu/inorder/resources/branch_predictor.hh"
 
 using namespace std;
diff --git a/src/cpu/inorder/resources/cache_unit.cc b/src/cpu/inorder/resources/cache_unit.cc
index 5677810f6..eb66e10f8 100644
--- a/src/cpu/inorder/resources/cache_unit.cc
+++ b/src/cpu/inorder/resources/cache_unit.cc
@@ -31,10 +31,12 @@
 
 #include <vector>
 #include <list>
+
 #include "arch/isa_traits.hh"
 #include "arch/locked_mem.hh"
 #include "arch/utility.hh"
 #include "arch/predecoder.hh"
+#include "config/the_isa.hh"
 #include "cpu/inorder/resources/cache_unit.hh"
 #include "cpu/inorder/pipeline_traits.hh"
 #include "cpu/inorder/cpu.hh"
diff --git a/src/cpu/inorder/resources/cache_unit.hh b/src/cpu/inorder/resources/cache_unit.hh
index 8946ad5d3..c467e9771 100644
--- a/src/cpu/inorder/resources/cache_unit.hh
+++ b/src/cpu/inorder/resources/cache_unit.hh
@@ -36,17 +36,17 @@
 #include <list>
 #include <string>
 
-#include "arch/tlb.hh"
 #include "arch/predecoder.hh"
-#include "cpu/inorder/resource.hh"
+#include "arch/tlb.hh"
+#include "config/the_isa.hh"
 #include "cpu/inorder/inorder_dyn_inst.hh"
+#include "cpu/inorder/pipeline_traits.hh"
+#include "cpu/inorder/resource.hh"
 #include "mem/packet.hh"
 #include "mem/packet_access.hh"
 #include "mem/port.hh"
-#include "cpu/inorder/pipeline_traits.hh"
-#include "sim/sim_object.hh"
-
 #include "params/InOrderCPU.hh"
+#include "sim/sim_object.hh"
 
 class CacheRequest;
 typedef CacheRequest* CacheReqPtr;
diff --git a/src/cpu/inorder/resources/decode_unit.cc b/src/cpu/inorder/resources/decode_unit.cc
index 033c318f2..33f5aba1a 100644
--- a/src/cpu/inorder/resources/decode_unit.cc
+++ b/src/cpu/inorder/resources/decode_unit.cc
@@ -29,6 +29,7 @@
  *
  */
 
+#include "config/the_isa.hh"
 #include "cpu/inorder/resources/decode_unit.hh"
 
 using namespace TheISA;
diff --git a/src/cpu/inorder/resources/fetch_seq_unit.cc b/src/cpu/inorder/resources/fetch_seq_unit.cc
index bc809b040..1d0b92075 100644
--- a/src/cpu/inorder/resources/fetch_seq_unit.cc
+++ b/src/cpu/inorder/resources/fetch_seq_unit.cc
@@ -29,6 +29,7 @@
  *
  */
 
+#include "config/the_isa.hh"
 #include "cpu/inorder/resources/fetch_seq_unit.hh"
 #include "cpu/inorder/resource_pool.hh"
 
diff --git a/src/cpu/inorder/resources/fetch_seq_unit.hh b/src/cpu/inorder/resources/fetch_seq_unit.hh
index 3e18d47cb..a4495564b 100644
--- a/src/cpu/inorder/resources/fetch_seq_unit.hh
+++ b/src/cpu/inorder/resources/fetch_seq_unit.hh
@@ -36,6 +36,7 @@
 #include <list>
 #include <string>
 
+#include "config/the_isa.hh"
 #include "cpu/inorder/resource.hh"
 #include "cpu/inorder/inorder_dyn_inst.hh"
 #include "cpu/inorder/pipeline_traits.hh"
diff --git a/src/cpu/inorder/resources/inst_buffer.cc b/src/cpu/inorder/resources/inst_buffer.cc
index 21df1d053..bb308b0ea 100644
--- a/src/cpu/inorder/resources/inst_buffer.cc
+++ b/src/cpu/inorder/resources/inst_buffer.cc
@@ -31,7 +31,9 @@
 
 #include <vector>
 #include <list>
+
 #include "arch/isa_traits.hh"
+#include "config/the_isa.hh"
 #include "cpu/inorder/pipeline_traits.hh"
 #include "cpu/inorder/resources/inst_buffer.hh"
 #include "cpu/inorder/cpu.hh"
diff --git a/src/cpu/inorder/resources/inst_buffer_new.cc b/src/cpu/inorder/resources/inst_buffer_new.cc
index cc534ef3e..2e5a9666a 100644
--- a/src/cpu/inorder/resources/inst_buffer_new.cc
+++ b/src/cpu/inorder/resources/inst_buffer_new.cc
@@ -31,7 +31,9 @@
 
 #include <vector>
 #include <list>
+
 #include "arch/isa_traits.hh"
+#include "config/the_isa.hh"
 #include "cpu/inorder/pipeline_traits.hh"
 #include "cpu/inorder/resources/inst_buffer.hh"
 #include "cpu/inorder/cpu.hh"
diff --git a/src/cpu/inorder/resources/mult_div_unit.cc b/src/cpu/inorder/resources/mult_div_unit.cc
index 7592c0260..e7bd6750f 100644
--- a/src/cpu/inorder/resources/mult_div_unit.cc
+++ b/src/cpu/inorder/resources/mult_div_unit.cc
@@ -91,7 +91,32 @@ MultDivUnit::freeSlot(int slot_idx)
     Resource::freeSlot(slot_idx);    
 }
 
-
+//@TODO: Should we push this behavior into base-class to generically
+//       accomodate all multicyle resources?
+void
+MultDivUnit::requestAgain(DynInstPtr inst, bool &service_request)
+{
+    ResReqPtr mult_div_req = findRequest(inst);
+    assert(mult_div_req);
+
+    service_request = true;
+
+    // Check to see if this instruction is requesting the same command
+    // or a different one
+    if (mult_div_req->cmd != inst->resSched.top()->cmd) {
+        // If different, then update command in the request
+        mult_div_req->cmd = inst->resSched.top()->cmd;
+        DPRINTF(InOrderMDU,
+                "[tid:%i]: [sn:%i]: Updating the command for this instruction\n",
+                inst->readTid(), inst->seqNum);
+    } else {
+        // If same command, just check to see if memory access was completed
+        // but dont try to re-execute
+        DPRINTF(InOrderMDU,
+                "[tid:%i]: [sn:%i]: requesting this resource again\n",
+                inst->readTid(), inst->seqNum);
+    }
+}
 int
 MultDivUnit::getSlot(DynInstPtr inst)
 {
@@ -232,8 +257,13 @@ MultDivUnit::execute(int slot_num)
         //      counting down the time
         {
             DPRINTF(InOrderMDU, "End MDU called ...\n");    
-            if (mult_div_req->getInst()->isExecuted())
+            if (mult_div_req->getInst()->isExecuted()) {
+                DPRINTF(InOrderMDU, "Mult/Div finished.\n");                    
                 mult_div_req->done();            
+            } else {                
+                mult_div_req->setCompleted(false);
+            }
+            
         }
         break;
 
diff --git a/src/cpu/inorder/resources/mult_div_unit.hh b/src/cpu/inorder/resources/mult_div_unit.hh
index 76180714c..d3dd0260d 100644
--- a/src/cpu/inorder/resources/mult_div_unit.hh
+++ b/src/cpu/inorder/resources/mult_div_unit.hh
@@ -82,6 +82,8 @@ class MultDivUnit : public Resource {
     /** Register extra resource stats */
     virtual void regStats();
 
+    void requestAgain(DynInstPtr inst, bool &try_request);
+
   protected:
     /** Latency & Repeat Rate for Multiply Insts */
     unsigned multRepeatRate;
diff --git a/src/cpu/inorder/resources/tlb_unit.cc b/src/cpu/inorder/resources/tlb_unit.cc
index 95bade36a..0410d6b24 100644
--- a/src/cpu/inorder/resources/tlb_unit.cc
+++ b/src/cpu/inorder/resources/tlb_unit.cc
@@ -31,7 +31,9 @@
 
 #include <vector>
 #include <list>
+
 #include "arch/isa_traits.hh"
+#include "config/the_isa.hh"
 #include "cpu/inorder/pipeline_traits.hh"
 #include "cpu/inorder/first_stage.hh"
 #include "cpu/inorder/resources/tlb_unit.hh"
diff --git a/src/cpu/inorder/resources/tlb_unit.hh b/src/cpu/inorder/resources/tlb_unit.hh
index 1c08bd822..5c62c7751 100644
--- a/src/cpu/inorder/resources/tlb_unit.hh
+++ b/src/cpu/inorder/resources/tlb_unit.hh
@@ -36,6 +36,7 @@
 #include <list>
 #include <string>
 
+#include "config/the_isa.hh"
 #include "cpu/inorder/resources/inst_buffer.hh"
 #include "cpu/inorder/inorder_dyn_inst.hh"
 #include "cpu/inorder/pipeline_traits.hh"
diff --git a/src/cpu/inorder/resources/use_def.cc b/src/cpu/inorder/resources/use_def.cc
index 2f1652c08..36392d054 100644
--- a/src/cpu/inorder/resources/use_def.cc
+++ b/src/cpu/inorder/resources/use_def.cc
@@ -31,7 +31,9 @@
 
 #include <vector>
 #include <list>
+
 #include "arch/isa_traits.hh"
+#include "config/the_isa.hh"
 #include "cpu/inorder/pipeline_traits.hh"
 #include "cpu/inorder/resources/use_def.hh"
 #include "cpu/inorder/cpu.hh"
diff --git a/src/cpu/inorder/thread_context.cc b/src/cpu/inorder/thread_context.cc
index fe1a0faa1..41d16b633 100644
--- a/src/cpu/inorder/thread_context.cc
+++ b/src/cpu/inorder/thread_context.cc
@@ -30,23 +30,77 @@
  */
 
 #include "arch/isa_traits.hh"
+#include "config/the_isa.hh"
 #include "cpu/exetrace.hh"
 #include "cpu/inorder/thread_context.hh"
 
 using namespace TheISA;
 
+#if FULL_SYSTEM
+
+VirtualPort *
+InOrderThreadContext::getVirtPort()
+{
+    return thread->getVirtPort();
+}
+
+
+void
+InOrderThreadContext::dumpFuncProfile()
+{
+    thread->dumpFuncProfile();
+}
+
+
+Tick
+InOrderThreadContext::readLastActivate()
+{
+    return thread->lastActivate;
+}
+
+
+Tick
+InOrderThreadContext::readLastSuspend()
+{
+    return thread->lastSuspend;
+}
+
+
+void
+InOrderThreadContext::profileClear()
+{
+    thread->profileClear();
+}
+
+
+void
+InOrderThreadContext::profileSample()
+{
+    thread->profileSample();
+}
+#endif
+
 void
 InOrderThreadContext::takeOverFrom(ThreadContext *old_context)
 {
     // some things should already be set up
+    assert(getSystemPtr() == old_context->getSystemPtr());
+#if !FULL_SYSTEM
     assert(getProcessPtr() == old_context->getProcessPtr());
+#endif
+
+
 
     // copy over functional state
     setStatus(old_context->status());
     copyArchRegs(old_context);
 
+#if !FULL_SYSTEM
     thread->funcExeInst = old_context->readFuncExeInst();
+#endif
+ 
     old_context->setStatus(ThreadContext::Halted);
+
     thread->inSyscall = false;
     thread->trapPending = false;
 }
@@ -97,8 +151,8 @@ void
 InOrderThreadContext::regStats(const std::string &name)
 {
 #if FULL_SYSTEM
-    thread->kernelStats = new Kernel::Statistics(cpu->system);
-    thread->kernelStats->regStats(name + ".kern");
+    //thread->kernelStats = new Kernel::Statistics(cpu->system);
+    //thread->kernelStats->regStats(name + ".kern");
 #endif
     ;
 }
@@ -107,22 +161,14 @@ InOrderThreadContext::regStats(const std::string &name)
 void
 InOrderThreadContext::serialize(std::ostream &os)
 {
-#if FULL_SYSTEM
-    if (thread->kernelStats)
-        thread->kernelStats->serialize(os);
-#endif
-    ;
+    panic("serialize unimplemented");
 }
 
 
 void
 InOrderThreadContext::unserialize(Checkpoint *cp, const std::string &section)
 {
-#if FULL_SYSTEM
-    if (thread->kernelStats)
-        thread->kernelStats->unserialize(cp, section);
-#endif
-    ;
+    panic("unserialize unimplemented");    
 }
 
 TheISA::MachInst
diff --git a/src/cpu/inorder/thread_context.hh b/src/cpu/inorder/thread_context.hh
index 327f8ac71..820f3077f 100644
--- a/src/cpu/inorder/thread_context.hh
+++ b/src/cpu/inorder/thread_context.hh
@@ -32,6 +32,7 @@
 #ifndef __CPU_INORDER_THREAD_CONTEXT_HH__
 #define __CPU_INORDER_THREAD_CONTEXT_HH__
 
+#include "config/the_isa.hh"
 #include "cpu/exetrace.hh"
 #include "cpu/thread_context.hh"
 #include "cpu/inorder/thread_state.hh"
@@ -101,10 +102,48 @@ class InOrderThreadContext : public ThreadContext
 
     virtual void setNextMicroPC(uint64_t val) { };
 
+#if FULL_SYSTEM
+    /** Returns a pointer to physical memory. */
+    virtual PhysicalMemory *getPhysMemPtr() 
+    { assert(0); return 0; /*return cpu->physmem;*/ }
+
+    /** Returns a pointer to this thread's kernel statistics. */
+    virtual TheISA::Kernel::Statistics *getKernelStats()
+    { return thread->kernelStats; }
+
+    virtual FunctionalPort *getPhysPort() { return thread->getPhysPort(); }
+
+    virtual VirtualPort *getVirtPort();
+
+    virtual void connectMemPorts(ThreadContext *tc) { thread->connectMemPorts(tc); }
+
+    /** Dumps the function profiling information.
+     * @todo: Implement.
+     */
+    virtual void dumpFuncProfile();
+
+    /** Reads the last tick that this thread was activated on. */
+    virtual Tick readLastActivate();
+    /** Reads the last tick that this thread was suspended on. */
+    virtual Tick readLastSuspend();
+
+    /** Clears the function profiling information. */
+    virtual void profileClear();
+
+    /** Samples the function profiling information. */
+    virtual void profileSample();
+
+    /** Returns pointer to the quiesce event. */
+    virtual EndQuiesceEvent *getQuiesceEvent()
+    {
+        return this->thread->quiesceEvent;
+    }
+#else
     virtual TranslatingPort *getMemPort() { return thread->getMemPort(); }
 
     /** Returns a pointer to this thread's process. */
     virtual Process *getProcessPtr() { return thread->getProcessPtr(); }
+#endif
 
     /** Returns this thread's status. */
     virtual Status status() const { return thread->status(); }
@@ -232,9 +271,11 @@ class InOrderThreadContext : public ThreadContext
      * misspeculating, this is set as false. */
     virtual bool misspeculating() { return false; }
 
+#if !FULL_SYSTEM
     /** Executes a syscall in SE mode. */
     virtual void syscall(int64_t callnum)
     { return cpu->syscall(callnum, thread->readTid()); }
+#endif
 
     /** Reads the funcExeInst counter. */
     virtual Counter readFuncExeInst() { return thread->funcExeInst; }
diff --git a/src/cpu/inorder/thread_state.cc b/src/cpu/inorder/thread_state.cc
new file mode 100644
index 000000000..b3a54efb1
--- /dev/null
+++ b/src/cpu/inorder/thread_state.cc
@@ -0,0 +1,47 @@
+/*
+ * Copyright (c) 2007 MIPS Technologies, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met: redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer;
+ * redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution;
+ * neither the name of the copyright holders nor the names of its
+ * contributors may be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * Authors: Korey Sewell
+ *
+ */
+
+#include "arch/isa_traits.hh"
+#include "cpu/exetrace.hh"
+#include "cpu/inorder/thread_state.hh"
+#include "cpu/inorder/cpu.hh"
+
+using namespace TheISA;
+
+#if FULL_SYSTEM
+void 
+InOrderThreadState::dumpFuncProfile()    
+{
+    std::ostream *os = simout.create(csprintf("profile.%s.dat", cpu->name()));
+    profile->dump(tc, *os);
+}
+#endif
+
diff --git a/src/cpu/inorder/thread_state.hh b/src/cpu/inorder/thread_state.hh
index 9b3b39fcb..422df30aa 100644
--- a/src/cpu/inorder/thread_state.hh
+++ b/src/cpu/inorder/thread_state.hh
@@ -33,13 +33,23 @@
 
 #include "arch/faults.hh"
 #include "arch/isa_traits.hh"
+#include "base/callback.hh"
+#include "base/output.hh"
 #include "cpu/thread_context.hh"
 #include "cpu/thread_state.hh"
+#include "sim/sim_exit.hh"
 
 class Event;
+class InOrderCPU;
+
+#if FULL_SYSTEM
+class EndQuiesceEvent;
+class FunctionProfile;
+class ProfileNode;
+#else
 class FunctionalMemory;
 class Process;
-class InOrderCPU;
+#endif
 
 /**
  * Class that has various thread state, such as the status, the
@@ -66,16 +76,28 @@ class InOrderThreadState : public ThreadState {
      */
     bool trapPending;
 
-
+#if FULL_SYSTEM
+    InOrderThreadState(InOrderCPU *_cpu, ThreadID _thread_num)
+        : ThreadState(reinterpret_cast<BaseCPU*>(_cpu), _thread_num),
+          cpu(_cpu), inSyscall(0), trapPending(0)
+    { }
+#else
     InOrderThreadState(InOrderCPU *_cpu, ThreadID _thread_num,
                        Process *_process)
-        : ThreadState(reinterpret_cast<BaseCPU*>(_cpu), 0/*_thread_num*/,
+        : ThreadState(reinterpret_cast<BaseCPU*>(_cpu), _thread_num,
                       _process),
           cpu(_cpu), inSyscall(0), trapPending(0)
     { }
+#endif
 
+#if !FULL_SYSTEM
     /** Handles the syscall. */
     void syscall(int64_t callnum) { process->syscall(callnum, tc); }
+#endif
+
+#if FULL_SYSTEM
+    void dumpFuncProfile();    
+#endif
 
     /** Pointer to the ThreadContext of this thread. */
     ThreadContext *tc;
@@ -83,7 +105,7 @@ class InOrderThreadState : public ThreadState {
     /** Returns a pointer to the TC of this thread. */
     ThreadContext *getTC() { return tc; }
 
-  int readTid() { return 0; }
+    int readTid() { return threadId(); }
 
     /** Pointer to the last graduated instruction in the thread */
     //DynInstPtr lastGradInst;
diff --git a/src/cpu/inst_seq.hh b/src/cpu/inst_seq.hh
index 21e04ed25..b5feaf584 100644
--- a/src/cpu/inst_seq.hh
+++ b/src/cpu/inst_seq.hh
@@ -32,6 +32,8 @@
 #ifndef __STD_TYPES_HH__
 #define __STD_TYPES_HH__
 
+#include "base/types.hh"
+
 // inst sequence type, used to order instructions in the ready list,
 // if this rolls over the ready list order temporarily will get messed
 // up, but execution will continue and complete correctly
diff --git a/src/cpu/inteltrace.cc b/src/cpu/inteltrace.cc
index 145075dc1..ec51b80e7 100644
--- a/src/cpu/inteltrace.cc
+++ b/src/cpu/inteltrace.cc
@@ -33,6 +33,7 @@
 
 #include <iomanip>
 
+#include "config/the_isa.hh"
 #include "cpu/exetrace.hh"
 #include "cpu/inteltrace.hh"
 #include "cpu/static_inst.hh"
diff --git a/src/cpu/legiontrace.cc b/src/cpu/legiontrace.cc
index 5face4391..1390d0807 100644
--- a/src/cpu/legiontrace.cc
+++ b/src/cpu/legiontrace.cc
@@ -31,7 +31,7 @@
  *          Steve Raasch
  */
 
-#include "arch/isa_specific.hh"
+#include "config/the_isa.hh"
 #if THE_ISA != SPARC_ISA
     #error Legion tracing only works with SPARC simulations!
 #endif
@@ -41,10 +41,12 @@
     #error Legion tracing only works in full system!
 #endif
 
-#include <iomanip>
 #include <sys/ipc.h>
 #include <sys/shm.h>
 
+#include <cstdio>
+#include <iomanip>
+
 #include "arch/sparc/predecoder.hh"
 #include "arch/sparc/registers.hh"
 #include "arch/sparc/utility.hh"
diff --git a/src/cpu/memtest/MemTest.py b/src/cpu/memtest/MemTest.py
index 629fd4877..8e1b3a8d0 100644
--- a/src/cpu/memtest/MemTest.py
+++ b/src/cpu/memtest/MemTest.py
@@ -29,7 +29,6 @@
 from MemObject import MemObject
 from m5.params import *
 from m5.proxy import *
-from m5 import build_env
 
 class MemTest(MemObject):
     type = 'MemTest'
diff --git a/src/cpu/o3/O3CPU.py b/src/cpu/o3/O3CPU.py
index 56e537ad2..3f2210e44 100644
--- a/src/cpu/o3/O3CPU.py
+++ b/src/cpu/o3/O3CPU.py
@@ -26,21 +26,21 @@
 #
 # Authors: Kevin Lim
 
+from m5.defines import buildEnv
 from m5.params import *
 from m5.proxy import *
-from m5 import build_env
 from BaseCPU import BaseCPU
 from FUPool import *
 
-if build_env['USE_CHECKER']:
+if buildEnv['USE_CHECKER']:
     from O3Checker import O3Checker
 
 class DerivO3CPU(BaseCPU):
     type = 'DerivO3CPU'
     activity = Param.Unsigned(0, "Initial count")
 
-    if build_env['USE_CHECKER']:
-        if not build_env['FULL_SYSTEM']:
+    if buildEnv['USE_CHECKER']:
+        if not buildEnv['FULL_SYSTEM']:
             checker = Param.BaseCPU(O3Checker(workload=Parent.workload,
                                               exitOnError=False,
                                               updateOnError=True,
diff --git a/src/cpu/o3/O3Checker.py b/src/cpu/o3/O3Checker.py
index edc6dc9b6..d0c4ce537 100644
--- a/src/cpu/o3/O3Checker.py
+++ b/src/cpu/o3/O3Checker.py
@@ -27,7 +27,6 @@
 # Authors: Nathan Binkert
 
 from m5.params import *
-from m5 import build_env
 from BaseCPU import BaseCPU
 
 class O3Checker(BaseCPU):
diff --git a/src/cpu/o3/bpred_unit_impl.hh b/src/cpu/o3/bpred_unit_impl.hh
index 1378ac135..ed3471761 100644
--- a/src/cpu/o3/bpred_unit_impl.hh
+++ b/src/cpu/o3/bpred_unit_impl.hh
@@ -28,16 +28,16 @@
  * Authors: Kevin Lim
  */
 
+#include <algorithm>
+
 #include "arch/types.hh"
 #include "arch/isa_traits.hh"
 #include "base/trace.hh"
 #include "base/traceflags.hh"
+#include "config/the_isa.hh"
 #include "cpu/o3/bpred_unit.hh"
-
 #include "params/DerivO3CPU.hh"
 
-#include <algorithm>
-
 template<class Impl>
 BPredUnit<Impl>::BPredUnit(DerivO3CPUParams *params)
     : _name(params->name + ".BPredUnit"),
diff --git a/src/cpu/o3/commit_impl.hh b/src/cpu/o3/commit_impl.hh
index 7286f1b6f..cb5f23814 100644
--- a/src/cpu/o3/commit_impl.hh
+++ b/src/cpu/o3/commit_impl.hh
@@ -37,6 +37,7 @@
 #include "base/loader/symtab.hh"
 #include "base/timebuf.hh"
 #include "config/full_system.hh"
+#include "config/the_isa.hh"
 #include "config/use_checker.hh"
 #include "cpu/exetrace.hh"
 #include "cpu/o3/commit.hh"
@@ -1075,9 +1076,11 @@ DefaultCommit<Impl>::commitHead(DynInstPtr &head_inst, unsigned inst_num)
         commitStatus[tid] = TrapPending;
 
         if (head_inst->traceData) {
-            head_inst->traceData->setFetchSeq(head_inst->seqNum);
-            head_inst->traceData->setCPSeq(thread[tid]->numInst);
-            head_inst->traceData->dump();
+            if (DTRACE(ExecFaulting)) {
+                head_inst->traceData->setFetchSeq(head_inst->seqNum);
+                head_inst->traceData->setCPSeq(thread[tid]->numInst);
+                head_inst->traceData->dump();
+            }
             delete head_inst->traceData;
             head_inst->traceData = NULL;
         }
diff --git a/src/cpu/o3/cpu.cc b/src/cpu/o3/cpu.cc
index 6722941e4..2a4e0176a 100644
--- a/src/cpu/o3/cpu.cc
+++ b/src/cpu/o3/cpu.cc
@@ -30,8 +30,8 @@
  */
 
 #include "config/full_system.hh"
+#include "config/the_isa.hh"
 #include "config/use_checker.hh"
-
 #include "cpu/activity.hh"
 #include "cpu/simple_thread.hh"
 #include "cpu/thread_context.hh"
@@ -200,7 +200,6 @@ FullO3CPU<Impl>::FullO3CPU(DerivO3CPUParams *params)
       globalSeqNum(1),
 #if FULL_SYSTEM
       system(params->system),
-      physmem(system->physmem),
 #endif // FULL_SYSTEM
       drainCount(0),
       deferRegistration(params->defer_registration)
diff --git a/src/cpu/o3/cpu.hh b/src/cpu/o3/cpu.hh
index 0cc8eab78..2ea918983 100644
--- a/src/cpu/o3/cpu.hh
+++ b/src/cpu/o3/cpu.hh
@@ -42,6 +42,7 @@
 #include "base/statistics.hh"
 #include "base/timebuf.hh"
 #include "config/full_system.hh"
+#include "config/the_isa.hh"
 #include "config/use_checker.hh"
 #include "cpu/activity.hh"
 #include "cpu/base.hh"
@@ -668,9 +669,6 @@ class FullO3CPU : public BaseO3CPU
 #if FULL_SYSTEM
     /** Pointer to the system. */
     System *system;
-
-    /** Pointer to physical memory. */
-    PhysicalMemory *physmem;
 #endif
 
     /** Event to call process() on once draining has completed. */
diff --git a/src/cpu/o3/decode_impl.hh b/src/cpu/o3/decode_impl.hh
index 86f87991c..1b76de132 100644
--- a/src/cpu/o3/decode_impl.hh
+++ b/src/cpu/o3/decode_impl.hh
@@ -28,6 +28,7 @@
  * Authors: Kevin Lim
  */
 
+#include "config/the_isa.hh"
 #include "cpu/o3/decode.hh"
 #include "params/DerivO3CPU.hh"
 
diff --git a/src/cpu/o3/dyn_inst.hh b/src/cpu/o3/dyn_inst.hh
index 3ef42e91f..e1279f82b 100644
--- a/src/cpu/o3/dyn_inst.hh
+++ b/src/cpu/o3/dyn_inst.hh
@@ -32,6 +32,7 @@
 #define __CPU_O3_DYN_INST_HH__
 
 #include "arch/isa_traits.hh"
+#include "config/the_isa.hh"
 #include "cpu/base_dyn_inst.hh"
 #include "cpu/inst_seq.hh"
 #include "cpu/o3/cpu.hh"
diff --git a/src/cpu/o3/fetch.hh b/src/cpu/o3/fetch.hh
index 9cbc50899..425c34428 100644
--- a/src/cpu/o3/fetch.hh
+++ b/src/cpu/o3/fetch.hh
@@ -36,6 +36,7 @@
 #include "arch/predecoder.hh"
 #include "base/statistics.hh"
 #include "base/timebuf.hh"
+#include "config/the_isa.hh"
 #include "cpu/pc_event.hh"
 #include "mem/packet.hh"
 #include "mem/port.hh"
diff --git a/src/cpu/o3/fetch_impl.hh b/src/cpu/o3/fetch_impl.hh
index 3781113bd..e6815ef8a 100644
--- a/src/cpu/o3/fetch_impl.hh
+++ b/src/cpu/o3/fetch_impl.hh
@@ -35,6 +35,7 @@
 #include "arch/isa_traits.hh"
 #include "arch/utility.hh"
 #include "base/types.hh"
+#include "config/the_isa.hh"
 #include "config/use_checker.hh"
 #include "cpu/checker/cpu.hh"
 #include "cpu/exetrace.hh"
@@ -1263,6 +1264,8 @@ DefaultFetch<Impl>::fetch(bool &status_change)
         toDecode->insts[numInst] = instruction;
         toDecode->size++;
 
+        wroteToTimeBuffer = true;
+
         DPRINTF(Fetch, "[tid:%i]: Blocked, need to handle the trap.\n",tid);
 
         fetchStatus[tid] = TrapPending;
diff --git a/src/cpu/o3/free_list.hh b/src/cpu/o3/free_list.hh
index e28c4910e..96289f641 100644
--- a/src/cpu/o3/free_list.hh
+++ b/src/cpu/o3/free_list.hh
@@ -38,6 +38,7 @@
 #include "base/misc.hh"
 #include "base/trace.hh"
 #include "base/traceflags.hh"
+#include "config/the_isa.hh"
 #include "cpu/o3/comm.hh"
 
 /**
diff --git a/src/cpu/o3/iew_impl.hh b/src/cpu/o3/iew_impl.hh
index ba29df196..751a26afd 100644
--- a/src/cpu/o3/iew_impl.hh
+++ b/src/cpu/o3/iew_impl.hh
@@ -35,6 +35,7 @@
 #include <queue>
 
 #include "base/timebuf.hh"
+#include "config/the_isa.hh"
 #include "cpu/o3/fu_pool.hh"
 #include "cpu/o3/iew.hh"
 #include "params/DerivO3CPU.hh"
diff --git a/src/cpu/o3/impl.hh b/src/cpu/o3/impl.hh
index 4b29b4daa..ffccd4a84 100644
--- a/src/cpu/o3/impl.hh
+++ b/src/cpu/o3/impl.hh
@@ -32,7 +32,7 @@
 #define __CPU_O3_IMPL_HH__
 
 #include "arch/isa_traits.hh"
-
+#include "config/the_isa.hh"
 #include "cpu/o3/cpu_policy.hh"
 
 
diff --git a/src/cpu/o3/lsq_unit.hh b/src/cpu/o3/lsq_unit.hh
index a917caef3..6ff36d929 100644
--- a/src/cpu/o3/lsq_unit.hh
+++ b/src/cpu/o3/lsq_unit.hh
@@ -40,6 +40,7 @@
 #include "arch/faults.hh"
 #include "arch/locked_mem.hh"
 #include "config/full_system.hh"
+#include "config/the_isa.hh"
 #include "base/fast_alloc.hh"
 #include "base/hashmap.hh"
 #include "cpu/inst_seq.hh"
diff --git a/src/cpu/o3/lsq_unit_impl.hh b/src/cpu/o3/lsq_unit_impl.hh
index edc8c9b3f..9ee1de45a 100644
--- a/src/cpu/o3/lsq_unit_impl.hh
+++ b/src/cpu/o3/lsq_unit_impl.hh
@@ -30,8 +30,8 @@
  */
 
 #include "arch/locked_mem.hh"
+#include "config/the_isa.hh"
 #include "config/use_checker.hh"
-
 #include "cpu/o3/lsq.hh"
 #include "cpu/o3/lsq_unit.hh"
 #include "base/str.hh"
diff --git a/src/cpu/o3/regfile.hh b/src/cpu/o3/regfile.hh
index d6beecdc5..e252fa362 100644
--- a/src/cpu/o3/regfile.hh
+++ b/src/cpu/o3/regfile.hh
@@ -32,18 +32,19 @@
 #ifndef __CPU_O3_REGFILE_HH__
 #define __CPU_O3_REGFILE_HH__
 
+#include <vector>
+
 #include "arch/isa_traits.hh"
 #include "arch/types.hh"
 #include "base/trace.hh"
 #include "config/full_system.hh"
+#include "config/the_isa.hh"
 #include "cpu/o3/comm.hh"
 
 #if FULL_SYSTEM
 #include "arch/kernel_stats.hh"
 #endif
 
-#include <vector>
-
 /**
  * Simple physical register file class.
  * Right now this is specific to Alpha until we decide if/how to make things
diff --git a/src/cpu/o3/rename.hh b/src/cpu/o3/rename.hh
index 734b63105..8c21dda0a 100644
--- a/src/cpu/o3/rename.hh
+++ b/src/cpu/o3/rename.hh
@@ -35,6 +35,7 @@
 
 #include "base/statistics.hh"
 #include "base/timebuf.hh"
+#include "config/the_isa.hh"
 
 class DerivO3CPUParams;
 
diff --git a/src/cpu/o3/rename_impl.hh b/src/cpu/o3/rename_impl.hh
index e4cc2674b..ce206435c 100644
--- a/src/cpu/o3/rename_impl.hh
+++ b/src/cpu/o3/rename_impl.hh
@@ -34,6 +34,7 @@
 #include "arch/isa_traits.hh"
 #include "arch/registers.hh"
 #include "config/full_system.hh"
+#include "config/the_isa.hh"
 #include "cpu/o3/rename.hh"
 #include "params/DerivO3CPU.hh"
 
diff --git a/src/cpu/o3/rename_map.hh b/src/cpu/o3/rename_map.hh
index 896c66f3e..51d8db4d8 100644
--- a/src/cpu/o3/rename_map.hh
+++ b/src/cpu/o3/rename_map.hh
@@ -39,8 +39,9 @@
 #include <utility>
 #include <vector>
 
-#include "cpu/o3/free_list.hh"
 #include "arch/types.hh"
+#include "config/the_isa.hh"
+#include "cpu/o3/free_list.hh"
 
 class SimpleRenameMap
 {
diff --git a/src/cpu/o3/rob.hh b/src/cpu/o3/rob.hh
index 657bc8d06..bdea07d1a 100644
--- a/src/cpu/o3/rob.hh
+++ b/src/cpu/o3/rob.hh
@@ -36,6 +36,8 @@
 #include <utility>
 #include <vector>
 
+#include "config/the_isa.hh"
+
 /**
  * ROB class.  The ROB is largely what drives squashing.
  */
diff --git a/src/cpu/o3/scoreboard.cc b/src/cpu/o3/scoreboard.cc
index e7f8b7949..ae1e13717 100644
--- a/src/cpu/o3/scoreboard.cc
+++ b/src/cpu/o3/scoreboard.cc
@@ -29,7 +29,7 @@
  *          Kevin Lim
  */
 
-#include "arch/isa_specific.hh"
+#include "config/the_isa.hh"
 #include "cpu/o3/scoreboard.hh"
 
 Scoreboard::Scoreboard(unsigned activeThreads,
diff --git a/src/cpu/o3/thread_context.hh b/src/cpu/o3/thread_context.hh
index ed5c6ac20..78b266014 100755
--- a/src/cpu/o3/thread_context.hh
+++ b/src/cpu/o3/thread_context.hh
@@ -31,6 +31,7 @@
 #ifndef __CPU_O3_THREAD_CONTEXT_HH__
 #define __CPU_O3_THREAD_CONTEXT_HH__
 
+#include "config/the_isa.hh"
 #include "cpu/thread_context.hh"
 #include "cpu/o3/isa_specific.hh"
 
@@ -90,9 +91,6 @@ class O3ThreadContext : public ThreadContext
     virtual System *getSystemPtr() { return cpu->system; }
 
 #if FULL_SYSTEM
-    /** Returns a pointer to physical memory. */
-    virtual PhysicalMemory *getPhysMemPtr() { return cpu->physmem; }
-
     /** Returns a pointer to this thread's kernel statistics. */
     virtual TheISA::Kernel::Statistics *getKernelStats()
     { return thread->kernelStats; }
diff --git a/src/cpu/o3/thread_context_impl.hh b/src/cpu/o3/thread_context_impl.hh
index e631c9244..940d460ce 100755
--- a/src/cpu/o3/thread_context_impl.hh
+++ b/src/cpu/o3/thread_context_impl.hh
@@ -30,6 +30,7 @@
  */
 
 #include "arch/registers.hh"
+#include "config/the_isa.hh"
 #include "cpu/o3/thread_context.hh"
 #include "cpu/quiesce_event.hh"
 
diff --git a/src/cpu/ozone/OzoneCPU.py b/src/cpu/ozone/OzoneCPU.py
index 37386898d..2c7b8475f 100644
--- a/src/cpu/ozone/OzoneCPU.py
+++ b/src/cpu/ozone/OzoneCPU.py
@@ -26,11 +26,11 @@
 #
 # Authors: Kevin Lim
 
+from m5.defines import buildEnv
 from m5.params import *
-from m5 import build_env
 from BaseCPU import BaseCPU
 
-if build_env['USE_CHECKER']:
+if buildEnv['USE_CHECKER']:
     from OzoneChecker import OzoneChecker
 
 class DerivOzoneCPU(BaseCPU):
@@ -38,7 +38,7 @@ class DerivOzoneCPU(BaseCPU):
 
     numThreads = Param.Unsigned("number of HW thread contexts")
 
-    if build_env['USE_CHECKER']:
+    if buildEnv['USE_CHECKER']:
         checker = Param.BaseCPU("Checker CPU")
 
     icache_port = Port("Instruction Port")
diff --git a/src/cpu/ozone/OzoneChecker.py b/src/cpu/ozone/OzoneChecker.py
index bfa39ead9..bbe46db18 100644
--- a/src/cpu/ozone/OzoneChecker.py
+++ b/src/cpu/ozone/OzoneChecker.py
@@ -27,7 +27,6 @@
 # Authors: Nathan Binkert
 
 from m5.params import *
-from m5 import build_env
 from BaseCPU import BaseCPU
 
 class OzoneChecker(BaseCPU):
diff --git a/src/cpu/ozone/SimpleOzoneCPU.py b/src/cpu/ozone/SimpleOzoneCPU.py
index 93603092b..d4620cd8e 100644
--- a/src/cpu/ozone/SimpleOzoneCPU.py
+++ b/src/cpu/ozone/SimpleOzoneCPU.py
@@ -26,8 +26,8 @@
 #
 # Authors: Kevin Lim
 
+from m5.defines import buildEnv
 from m5.params import *
-from m5 import build_env
 from BaseCPU import BaseCPU
 
 class SimpleOzoneCPU(BaseCPU):
@@ -35,7 +35,7 @@ class SimpleOzoneCPU(BaseCPU):
 
     numThreads = Param.Unsigned("number of HW thread contexts")
 
-    if not build_env['FULL_SYSTEM']:
+    if not buildEnv['FULL_SYSTEM']:
         mem = Param.FunctionalMemory(NULL, "memory")
 
     width = Param.Unsigned("Width")
diff --git a/src/cpu/ozone/cpu.hh b/src/cpu/ozone/cpu.hh
index 5e36332af..a16986c99 100644
--- a/src/cpu/ozone/cpu.hh
+++ b/src/cpu/ozone/cpu.hh
@@ -36,6 +36,7 @@
 #include "base/statistics.hh"
 #include "base/timebuf.hh"
 #include "config/full_system.hh"
+#include "config/the_isa.hh"
 #include "cpu/base.hh"
 #include "cpu/thread_context.hh"
 #include "cpu/inst_seq.hh"
diff --git a/src/cpu/ozone/cpu_impl.hh b/src/cpu/ozone/cpu_impl.hh
index f86b882d1..c09dd9046 100644
--- a/src/cpu/ozone/cpu_impl.hh
+++ b/src/cpu/ozone/cpu_impl.hh
@@ -34,6 +34,7 @@
 
 #include "arch/isa_traits.hh" // For MachInst
 #include "base/trace.hh"
+#include "config/the_isa.hh"
 #include "cpu/base.hh"
 #include "cpu/simple_thread.hh"
 #include "cpu/thread_context.hh"
diff --git a/src/cpu/ozone/dyn_inst.hh b/src/cpu/ozone/dyn_inst.hh
index a39f383ba..cca72ef18 100644
--- a/src/cpu/ozone/dyn_inst.hh
+++ b/src/cpu/ozone/dyn_inst.hh
@@ -34,6 +34,7 @@
 #include "arch/isa_traits.hh"
 #include "arch/types.hh"
 #include "config/full_system.hh"
+#include "config/the_isa.hh"
 #include "cpu/base_dyn_inst.hh"
 #include "cpu/inst_seq.hh"
 #include "cpu/ozone/cpu.hh"   // MUST include this
diff --git a/src/cpu/ozone/dyn_inst_impl.hh b/src/cpu/ozone/dyn_inst_impl.hh
index 8519917f5..bfefb9428 100644
--- a/src/cpu/ozone/dyn_inst_impl.hh
+++ b/src/cpu/ozone/dyn_inst_impl.hh
@@ -30,6 +30,7 @@
 
 #include "sim/faults.hh"
 #include "config/full_system.hh"
+#include "config/the_isa.hh"
 #include "cpu/ozone/dyn_inst.hh"
 
 #if FULL_SYSTEM
diff --git a/src/cpu/ozone/front_end.hh b/src/cpu/ozone/front_end.hh
index 38fc89e3f..3809db00d 100644
--- a/src/cpu/ozone/front_end.hh
+++ b/src/cpu/ozone/front_end.hh
@@ -35,6 +35,7 @@
 
 #include "arch/utility.hh"
 #include "base/timebuf.hh"
+#include "config/the_isa.hh"
 #include "cpu/inst_seq.hh"
 #include "cpu/o3/bpred_unit.hh"
 #include "cpu/ozone/rename_table.hh"
diff --git a/src/cpu/ozone/front_end_impl.hh b/src/cpu/ozone/front_end_impl.hh
index 516823b47..884136927 100644
--- a/src/cpu/ozone/front_end_impl.hh
+++ b/src/cpu/ozone/front_end_impl.hh
@@ -28,12 +28,12 @@
  * Authors: Kevin Lim
  */
 
-#include "config/use_checker.hh"
-
 #include "sim/faults.hh"
 #include "arch/isa_traits.hh"
 #include "arch/utility.hh"
 #include "base/statistics.hh"
+#include "config/the_isa.hh"
+#include "config/use_checker.hh"
 #include "cpu/thread_context.hh"
 #include "cpu/exetrace.hh"
 #include "cpu/ozone/front_end.hh"
diff --git a/src/cpu/ozone/inorder_back_end_impl.hh b/src/cpu/ozone/inorder_back_end_impl.hh
index 798b628d6..2d4d225c7 100644
--- a/src/cpu/ozone/inorder_back_end_impl.hh
+++ b/src/cpu/ozone/inorder_back_end_impl.hh
@@ -30,6 +30,7 @@
 
 #include "sim/faults.hh"
 #include "arch/types.hh"
+#include "config/the_isa.hh"
 #include "cpu/ozone/inorder_back_end.hh"
 #include "cpu/ozone/thread_state.hh"
 
diff --git a/src/cpu/ozone/lsq_unit.hh b/src/cpu/ozone/lsq_unit.hh
index 47be245e5..d8e402b65 100644
--- a/src/cpu/ozone/lsq_unit.hh
+++ b/src/cpu/ozone/lsq_unit.hh
@@ -38,6 +38,7 @@
 #include "arch/faults.hh"
 #include "arch/types.hh"
 #include "config/full_system.hh"
+#include "config/the_isa.hh"
 #include "base/hashmap.hh"
 #include "cpu/inst_seq.hh"
 #include "mem/mem_interface.hh"
diff --git a/src/cpu/ozone/lsq_unit_impl.hh b/src/cpu/ozone/lsq_unit_impl.hh
index 833aa0581..dd44adf6e 100644
--- a/src/cpu/ozone/lsq_unit_impl.hh
+++ b/src/cpu/ozone/lsq_unit_impl.hh
@@ -30,6 +30,7 @@
 
 #include "arch/faults.hh"
 #include "base/str.hh"
+#include "config/the_isa.hh"
 #include "cpu/ozone/lsq_unit.hh"
 
 template <class Impl>
diff --git a/src/cpu/ozone/lw_back_end_impl.hh b/src/cpu/ozone/lw_back_end_impl.hh
index 86d4531a0..cbc386cb0 100644
--- a/src/cpu/ozone/lw_back_end_impl.hh
+++ b/src/cpu/ozone/lw_back_end_impl.hh
@@ -28,8 +28,8 @@
  * Authors: Kevin Lim
  */
 
+#include "config/the_isa.hh"
 #include "config/use_checker.hh"
-
 #include "cpu/ozone/lw_back_end.hh"
 #include "cpu/op_class.hh"
 
diff --git a/src/cpu/ozone/lw_lsq.hh b/src/cpu/ozone/lw_lsq.hh
index 6e9bb77af..ee0312969 100644
--- a/src/cpu/ozone/lw_lsq.hh
+++ b/src/cpu/ozone/lw_lsq.hh
@@ -39,6 +39,7 @@
 #include "arch/faults.hh"
 #include "arch/types.hh"
 #include "config/full_system.hh"
+#include "config/the_isa.hh"
 #include "base/fast_alloc.hh"
 #include "base/hashmap.hh"
 #include "cpu/inst_seq.hh"
diff --git a/src/cpu/ozone/lw_lsq_impl.hh b/src/cpu/ozone/lw_lsq_impl.hh
index 4d290a1e9..c714c5d38 100644
--- a/src/cpu/ozone/lw_lsq_impl.hh
+++ b/src/cpu/ozone/lw_lsq_impl.hh
@@ -28,10 +28,10 @@
  * Authors: Kevin Lim
  */
 
-#include "config/use_checker.hh"
-
 #include "arch/faults.hh"
 #include "base/str.hh"
+#include "config/the_isa.hh"
+#include "config/use_checker.hh"
 #include "cpu/ozone/lw_lsq.hh"
 #include "cpu/checker/cpu.hh"
 
diff --git a/src/cpu/ozone/rename_table.hh b/src/cpu/ozone/rename_table.hh
index 0b67d9635..9a5579158 100644
--- a/src/cpu/ozone/rename_table.hh
+++ b/src/cpu/ozone/rename_table.hh
@@ -32,6 +32,7 @@
 #define __CPU_OZONE_RENAME_TABLE_HH__
 
 #include "arch/isa_traits.hh"
+#include "config/the_isa.hh"
 
 /** Rename table that holds the rename of each architectural register to
  *  producing DynInst. Needs to support copying from one table to another.
diff --git a/src/cpu/ozone/rename_table_impl.hh b/src/cpu/ozone/rename_table_impl.hh
index 67bab7337..e8071e2b3 100644
--- a/src/cpu/ozone/rename_table_impl.hh
+++ b/src/cpu/ozone/rename_table_impl.hh
@@ -29,6 +29,8 @@
  */
 
 #include <cstdlib>  // Not really sure what to include to get NULL
+
+#include "config/the_isa.hh"
 #include "cpu/ozone/rename_table.hh"
 
 template <class Impl>
diff --git a/src/cpu/ozone/simple_params.hh b/src/cpu/ozone/simple_params.hh
index 7687fdf60..b241dea73 100644
--- a/src/cpu/ozone/simple_params.hh
+++ b/src/cpu/ozone/simple_params.hh
@@ -31,6 +31,7 @@
 #ifndef __CPU_OZONE_SIMPLE_PARAMS_HH__
 #define __CPU_OZONE_SIMPLE_PARAMS_HH__
 
+#include "config/the_isa.hh"
 #include "cpu/ozone/cpu.hh"
 
 //Forward declarations
diff --git a/src/cpu/ozone/thread_state.hh b/src/cpu/ozone/thread_state.hh
index 971fba886..638b9d86c 100644
--- a/src/cpu/ozone/thread_state.hh
+++ b/src/cpu/ozone/thread_state.hh
@@ -31,13 +31,14 @@
 #ifndef __CPU_OZONE_THREAD_STATE_HH__
 #define __CPU_OZONE_THREAD_STATE_HH__
 
-#include "sim/faults.hh"
-#include "arch/types.hh"
 #include "arch/regfile.hh"
+#include "arch/types.hh"
 #include "base/callback.hh"
 #include "base/output.hh"
+#include "config/the_isa.hh"
 #include "cpu/thread_context.hh"
 #include "cpu/thread_state.hh"
+#include "sim/faults.hh"
 #include "sim/process.hh"
 #include "sim/sim_exit.hh"
 
diff --git a/src/cpu/profile.hh b/src/cpu/profile.hh
index 9606ed24d..dd856b5a7 100644
--- a/src/cpu/profile.hh
+++ b/src/cpu/profile.hh
@@ -34,6 +34,7 @@
 #include <map>
 
 #include "arch/stacktrace.hh"
+#include "config/the_isa.hh"
 #include "cpu/static_inst.hh"
 #include "base/types.hh"
 
diff --git a/src/cpu/simple/AtomicSimpleCPU.py b/src/cpu/simple/AtomicSimpleCPU.py
index b7174bb43..3d72f4098 100644
--- a/src/cpu/simple/AtomicSimpleCPU.py
+++ b/src/cpu/simple/AtomicSimpleCPU.py
@@ -27,7 +27,6 @@
 # Authors: Nathan Binkert
 
 from m5.params import *
-from m5 import build_env
 from BaseSimpleCPU import BaseSimpleCPU
 
 class AtomicSimpleCPU(BaseSimpleCPU):
diff --git a/src/cpu/simple/TimingSimpleCPU.py b/src/cpu/simple/TimingSimpleCPU.py
index ce6839241..6b83c41aa 100644
--- a/src/cpu/simple/TimingSimpleCPU.py
+++ b/src/cpu/simple/TimingSimpleCPU.py
@@ -27,7 +27,6 @@
 # Authors: Nathan Binkert
 
 from m5.params import *
-from m5 import build_env
 from BaseSimpleCPU import BaseSimpleCPU
 
 class TimingSimpleCPU(BaseSimpleCPU):
diff --git a/src/cpu/simple/atomic.cc b/src/cpu/simple/atomic.cc
index 83da618f8..05b4ca3e2 100644
--- a/src/cpu/simple/atomic.cc
+++ b/src/cpu/simple/atomic.cc
@@ -32,6 +32,7 @@
 #include "arch/mmaped_ipr.hh"
 #include "arch/utility.hh"
 #include "base/bigint.hh"
+#include "config/the_isa.hh"
 #include "cpu/exetrace.hh"
 #include "cpu/simple/atomic.hh"
 #include "mem/packet.hh"
@@ -170,6 +171,9 @@ AtomicSimpleCPU::AtomicSimpleCPU(AtomicSimpleCPUParams *p)
 
 AtomicSimpleCPU::~AtomicSimpleCPU()
 {
+    if (tickEvent.scheduled()) {
+        deschedule(tickEvent);
+    }
 }
 
 void
@@ -352,8 +356,14 @@ AtomicSimpleCPU::read(Addr addr, T &data, unsigned flags)
             recordEvent("Uncached Read");
 
         //If there's a fault, return it
-        if (fault != NoFault)
-            return fault;
+        if (fault != NoFault) {
+            if (req->isPrefetch()) {
+                return NoFault;
+            } else {
+                return fault;
+            }
+        }
+
         //If we don't need to access a second cache line, stop now.
         if (secondAddr <= addr)
         {
@@ -530,7 +540,11 @@ AtomicSimpleCPU::write(T data, Addr addr, unsigned flags, uint64_t *res)
                 assert(locked);
                 locked = false;
             }
-            return fault;
+            if (fault != NoFault && req->isPrefetch()) {
+                return NoFault;
+            } else {
+                return fault;
+            }
         }
 
         /*
diff --git a/src/cpu/simple/base.cc b/src/cpu/simple/base.cc
index 732bb637b..0104e1b1f 100644
--- a/src/cpu/simple/base.cc
+++ b/src/cpu/simple/base.cc
@@ -40,6 +40,7 @@
 #include "base/stats/events.hh"
 #include "base/trace.hh"
 #include "base/types.hh"
+#include "config/the_isa.hh"
 #include "cpu/base.hh"
 #include "cpu/exetrace.hh"
 #include "cpu/profile.hh"
diff --git a/src/cpu/simple/base.hh b/src/cpu/simple/base.hh
index 466d0d1c9..39961fb88 100644
--- a/src/cpu/simple/base.hh
+++ b/src/cpu/simple/base.hh
@@ -36,6 +36,7 @@
 #include "arch/predecoder.hh"
 #include "base/statistics.hh"
 #include "config/full_system.hh"
+#include "config/the_isa.hh"
 #include "cpu/base.hh"
 #include "cpu/simple_thread.hh"
 #include "cpu/pc_event.hh"
diff --git a/src/cpu/simple/timing.cc b/src/cpu/simple/timing.cc
index 672fd9414..6b22d2fcf 100644
--- a/src/cpu/simple/timing.cc
+++ b/src/cpu/simple/timing.cc
@@ -32,6 +32,7 @@
 #include "arch/mmaped_ipr.hh"
 #include "arch/utility.hh"
 #include "base/bigint.hh"
+#include "config/the_isa.hh"
 #include "cpu/exetrace.hh"
 #include "cpu/simple/timing.hh"
 #include "mem/packet.hh"
@@ -272,6 +273,8 @@ TimingSimpleCPU::sendData(Fault fault, RequestPtr req,
 {
     _status = Running;
     if (fault != NoFault) {
+        if (req->isPrefetch())
+            fault = NoFault;
         delete data;
         delete req;
 
@@ -314,6 +317,10 @@ TimingSimpleCPU::sendSplitData(Fault fault1, Fault fault2,
 {
     _status = Running;
     if (fault1 != NoFault || fault2 != NoFault) {
+        if (req1->isPrefetch())
+            fault1 = NoFault;
+        if (req2->isPrefetch())
+            fault2 = NoFault;
         delete data;
         delete req1;
         delete req2;
@@ -359,6 +366,8 @@ TimingSimpleCPU::sendSplitData(Fault fault1, Fault fault2,
 void
 TimingSimpleCPU::translationFault(Fault fault)
 {
+    // fault may be NoFault in cases where a fault is suppressed,
+    // for instance prefetches.
     numCycles += tickToCycles(curTick - previousTick);
     previousTick = curTick;
 
diff --git a/src/cpu/simple_thread.cc b/src/cpu/simple_thread.cc
index 22bc283a3..ad69719ee 100644
--- a/src/cpu/simple_thread.cc
+++ b/src/cpu/simple_thread.cc
@@ -34,6 +34,7 @@
 #include <string>
 
 #include "arch/isa_traits.hh"
+#include "config/the_isa.hh"
 #include "cpu/base.hh"
 #include "cpu/simple_thread.hh"
 #include "cpu/thread_context.hh"
@@ -198,6 +199,11 @@ SimpleThread::serialize(ostream &os)
     SERIALIZE_SCALAR(nextPC);
     SERIALIZE_SCALAR(nextNPC);
     // thread_num and cpu_id are deterministic from the config
+
+    // 
+    // Now must serialize all the ISA dependent state
+    //
+    isa.serialize(cpu, os);
 }
 
 
@@ -213,6 +219,11 @@ SimpleThread::unserialize(Checkpoint *cp, const std::string &section)
     UNSERIALIZE_SCALAR(nextPC);
     UNSERIALIZE_SCALAR(nextNPC);
     // thread_num and cpu_id are deterministic from the config
+
+    // 
+    // Now must unserialize all the ISA dependent state
+    //
+    isa.unserialize(cpu, cp, section);
 }
 
 #if FULL_SYSTEM
diff --git a/src/cpu/simple_thread.hh b/src/cpu/simple_thread.hh
index 8a44eba37..2d28607b4 100644
--- a/src/cpu/simple_thread.hh
+++ b/src/cpu/simple_thread.hh
@@ -39,6 +39,7 @@
 #include "arch/types.hh"
 #include "base/types.hh"
 #include "config/full_system.hh"
+#include "config/the_isa.hh"
 #include "cpu/thread_context.hh"
 #include "cpu/thread_state.hh"
 #include "mem/request.hh"
diff --git a/src/cpu/static_inst.hh b/src/cpu/static_inst.hh
index b1298e0e9..fdec09756 100644
--- a/src/cpu/static_inst.hh
+++ b/src/cpu/static_inst.hh
@@ -36,6 +36,7 @@
 
 #include "arch/isa_traits.hh"
 #include "arch/utility.hh"
+#include "config/the_isa.hh"
 #include "base/bitfield.hh"
 #include "base/hashmap.hh"
 #include "base/misc.hh"
diff --git a/src/cpu/thread_context.cc b/src/cpu/thread_context.cc
index ab105a435..f2083ef08 100644
--- a/src/cpu/thread_context.cc
+++ b/src/cpu/thread_context.cc
@@ -30,6 +30,7 @@
 
 #include "base/misc.hh"
 #include "base/trace.hh"
+#include "config/the_isa.hh"
 #include "cpu/thread_context.hh"
 
 void
diff --git a/src/cpu/thread_context.hh b/src/cpu/thread_context.hh
index 9e34204ef..78ecdacf2 100644
--- a/src/cpu/thread_context.hh
+++ b/src/cpu/thread_context.hh
@@ -35,6 +35,7 @@
 #include "arch/types.hh"
 #include "base/types.hh"
 #include "config/full_system.hh"
+#include "config/the_isa.hh"
 #include "mem/request.hh"
 #include "sim/byteswap.hh"
 #include "sim/faults.hh"
diff --git a/src/cpu/thread_state.hh b/src/cpu/thread_state.hh
index 5c7c0ea56..cf637aeda 100644
--- a/src/cpu/thread_state.hh
+++ b/src/cpu/thread_state.hh
@@ -32,6 +32,7 @@
 #define __CPU_THREAD_STATE_HH__
 
 #include "arch/types.hh"
+#include "config/the_isa.hh"
 #include "cpu/profile.hh"
 #include "cpu/thread_context.hh"
 #include "cpu/base.hh"