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authorNathan Binkert <nate@binkert.org>2009-04-21 15:40:25 -0700
committerNathan Binkert <nate@binkert.org>2009-04-21 15:40:25 -0700
commit50f1570352a036aed49a078b17fa1af54d0a1787 (patch)
tree25514def7207d0ce38f01ee7d87f160f04a9fe95 /src/cpu
parentfff9c93568d73dcb2d237f0386dc7323412ff710 (diff)
downloadgem5-50f1570352a036aed49a078b17fa1af54d0a1787.tar.xz
arm: Unify the ARM tlb. We forgot about this when we did the rest.
This code compiles, but there are no tests still
Diffstat (limited to 'src/cpu')
-rw-r--r--src/cpu/BaseCPU.py6
1 files changed, 3 insertions, 3 deletions
diff --git a/src/cpu/BaseCPU.py b/src/cpu/BaseCPU.py
index 3aa9b87bb..4661375ba 100644
--- a/src/cpu/BaseCPU.py
+++ b/src/cpu/BaseCPU.py
@@ -54,7 +54,7 @@ elif build_env['TARGET_ISA'] == 'mips':
if build_env['FULL_SYSTEM']:
from MipsInterrupts import MipsInterrupts
elif build_env['TARGET_ISA'] == 'arm':
- from ArmTLB import ArmDTB
+ from ArmTLB import ArmTLB
if build_env['FULL_SYSTEM']:
from ArmInterrupts import ArmInterrupts
@@ -109,8 +109,8 @@ class BaseCPU(MemObject):
MipsInterrupts(), "Interrupt Controller")
elif build_env['TARGET_ISA'] == 'arm':
UnifiedTLB = Param.Bool(True, "Is this a Unified TLB?")
- dtb = Param.ArmTLB(ArmDTB(), "Data TLB")
- itb = Param.ArmTLB(ArmITB(), "Instruction TLB")
+ dtb = Param.ArmTLB(ArmTLB(), "Data TLB")
+ itb = Param.ArmTLB(ArmTLB(), "Instruction TLB")
if build_env['FULL_SYSTEM']:
interrupts = Param.ArmInterrupts(
ArmInterrupts(), "Interrupt Controller")