tlb: Don't separate the TLB classes into an instruction TLB and a data TLB

18 files changed, 54 insertions, 59 deletions

diff --git a/src/cpu/BaseCPU.py b/src/cpu/BaseCPU.py
index f3688e991..ef777ac5b 100644
--- a/src/cpu/BaseCPU.py
+++ b/src/cpu/BaseCPU.py
@@ -38,19 +38,19 @@ import sys
 default_tracer = ExeTracer()
 
 if build_env['TARGET_ISA'] == 'alpha':
-    from AlphaTLB import AlphaDTB, AlphaITB
+    from AlphaTLB import AlphaTLB
     if build_env['FULL_SYSTEM']:
         from AlphaInterrupts import AlphaInterrupts
 elif build_env['TARGET_ISA'] == 'sparc':
-    from SparcTLB import SparcDTB, SparcITB
+    from SparcTLB import SparcTLB
     if build_env['FULL_SYSTEM']:
         from SparcInterrupts import SparcInterrupts
 elif build_env['TARGET_ISA'] == 'x86':
-    from X86TLB import X86DTB, X86ITB
+    from X86TLB import X86TLB
     if build_env['FULL_SYSTEM']:
         from X86LocalApic import X86LocalApic
 elif build_env['TARGET_ISA'] == 'mips':
-    from MipsTLB import MipsTLB,MipsDTB, MipsITB, MipsUTB
+    from MipsTLB import MipsTLB
     if build_env['FULL_SYSTEM']:
         from MipsInterrupts import MipsInterrupts
 elif build_env['TARGET_ISA'] == 'arm':
@@ -83,29 +83,27 @@ class BaseCPU(MemObject):
         workload = VectorParam.Process("processes to run")
 
     if build_env['TARGET_ISA'] == 'sparc':
-        dtb = Param.SparcDTB(SparcDTB(), "Data TLB")
-        itb = Param.SparcITB(SparcITB(), "Instruction TLB")
+        dtb = Param.SparcTLB(SparcTLB(), "Data TLB")
+        itb = Param.SparcTLB(SparcTLB(), "Instruction TLB")
         if build_env['FULL_SYSTEM']:
             interrupts = Param.SparcInterrupts(
                 SparcInterrupts(), "Interrupt Controller")
     elif build_env['TARGET_ISA'] == 'alpha':
-        dtb = Param.AlphaDTB(AlphaDTB(), "Data TLB")
-        itb = Param.AlphaITB(AlphaITB(), "Instruction TLB")
+        dtb = Param.AlphaTLB(AlphaTLB(size=64), "Data TLB")
+        itb = Param.AlphaTLB(AlphaTLB(size=48), "Instruction TLB")
         if build_env['FULL_SYSTEM']:
             interrupts = Param.AlphaInterrupts(
                 AlphaInterrupts(), "Interrupt Controller")
     elif build_env['TARGET_ISA'] == 'x86':
-        dtb = Param.X86DTB(X86DTB(), "Data TLB")
-        itb = Param.X86ITB(X86ITB(), "Instruction TLB")
+        dtb = Param.X86TLB(X86TLB(), "Data TLB")
+        itb = Param.X86TLB(X86TLB(), "Instruction TLB")
         if build_env['FULL_SYSTEM']:
             _localApic = X86LocalApic(pio_addr=0x2000000000000000)
             interrupts = \
                 Param.X86LocalApic(_localApic, "Interrupt Controller")
     elif build_env['TARGET_ISA'] == 'mips':
-        UnifiedTLB = Param.Bool(True, "Is this a Unified TLB?")
-        dtb = Param.MipsDTB(MipsDTB(), "Data TLB")
-        itb = Param.MipsITB(MipsITB(), "Instruction TLB")
-        tlb = Param.MipsUTB(MipsUTB(), "Unified TLB")
+        dtb = Param.MipsTLB(MipsTLB(), "Data TLB")
+        itb = Param.MipsTLB(MipsTLB(), "Instruction TLB")
         if build_env['FULL_SYSTEM']:
             interrupts = Param.MipsInterrupts(
                     MipsInterrupts(), "Interrupt Controller")
diff --git a/src/cpu/checker/cpu.hh b/src/cpu/checker/cpu.hh
index 0d3dddded..3b378700e 100644
--- a/src/cpu/checker/cpu.hh
+++ b/src/cpu/checker/cpu.hh
@@ -49,8 +49,7 @@
 #if FULL_SYSTEM
 namespace TheISA
 {
-    class ITB;
-    class DTB;
+    class TLB;
 }
 class Processor;
 class PhysicalMemory;
@@ -130,8 +129,8 @@ class CheckerCPU : public BaseCPU
 
     ThreadContext *tc;
 
-    TheISA::ITB *itb;
-    TheISA::DTB *dtb;
+    TheISA::TLB *itb;
+    TheISA::TLB *dtb;
 
 #if FULL_SYSTEM
     Addr dbg_vtophys(Addr addr);
diff --git a/src/cpu/checker/thread_context.hh b/src/cpu/checker/thread_context.hh
index 3c87f841f..6b21bf670 100644
--- a/src/cpu/checker/thread_context.hh
+++ b/src/cpu/checker/thread_context.hh
@@ -84,9 +84,9 @@ class CheckerThreadContext : public ThreadContext
 
     int cpuId() { return actualTC->cpuId(); }
 
-    TheISA::ITB *getITBPtr() { return actualTC->getITBPtr(); }
+    TheISA::TLB *getITBPtr() { return actualTC->getITBPtr(); }
 
-    TheISA::DTB *getDTBPtr() { return actualTC->getDTBPtr(); }
+    TheISA::TLB *getDTBPtr() { return actualTC->getDTBPtr(); }
 
 #if FULL_SYSTEM
     System *getSystemPtr() { return actualTC->getSystemPtr(); }
diff --git a/src/cpu/inorder/cpu.hh b/src/cpu/inorder/cpu.hh
index adcd28019..f30ef128b 100644
--- a/src/cpu/inorder/cpu.hh
+++ b/src/cpu/inorder/cpu.hh
@@ -103,8 +103,8 @@ class InOrderCPU : public BaseCPU
 
     Params *cpu_params;
 
-    TheISA::ITB * itb;
-    TheISA::DTB * dtb;
+    TheISA::TLB * itb;
+    TheISA::TLB * dtb;
 
   public:
     enum Status {
diff --git a/src/cpu/inorder/resources/tlb_unit.cc b/src/cpu/inorder/resources/tlb_unit.cc
index 8f8ba144e..b3757d707 100644
--- a/src/cpu/inorder/resources/tlb_unit.cc
+++ b/src/cpu/inorder/resources/tlb_unit.cc
@@ -99,7 +99,7 @@ TLBUnit::execute(int slot_idx)
         {
             tlb_req->fault =
                 this->cpu->itb->translateAtomic(tlb_req->memReq,
-                        cpu->thread[tid]->getTC());
+                        cpu->thread[tid]->getTC(), false, true);
 
             if (tlb_req->fault != NoFault) {
                 DPRINTF(InOrderTLB, "[tid:%i]: %s encountered while translating "
diff --git a/src/cpu/inorder/thread_context.hh b/src/cpu/inorder/thread_context.hh
index 2fb2ed85f..3a1cb1379 100644
--- a/src/cpu/inorder/thread_context.hh
+++ b/src/cpu/inorder/thread_context.hh
@@ -65,10 +65,10 @@ class InOrderThreadContext : public ThreadContext
 
 
     /** Returns a pointer to the ITB. */
-    TheISA::ITB *getITBPtr() { return cpu->itb; }
+    TheISA::TLB *getITBPtr() { return cpu->itb; }
 
     /** Returns a pointer to the DTB. */
-    TheISA::DTB *getDTBPtr() { return cpu->dtb; }
+    TheISA::TLB *getDTBPtr() { return cpu->dtb; }
 
     System *getSystemPtr() { return cpu->system; }
 
diff --git a/src/cpu/o3/cpu.hh b/src/cpu/o3/cpu.hh
index 942970f5f..9eead4f49 100644
--- a/src/cpu/o3/cpu.hh
+++ b/src/cpu/o3/cpu.hh
@@ -106,8 +106,8 @@ class FullO3CPU : public BaseO3CPU
         SwitchedOut
     };
 
-    TheISA::ITB * itb;
-    TheISA::DTB * dtb;
+    TheISA::TLB * itb;
+    TheISA::TLB * dtb;
 
     /** Overall CPU status. */
     Status _status;
diff --git a/src/cpu/o3/fetch_impl.hh b/src/cpu/o3/fetch_impl.hh
index 79a4f2b7a..f9cc78c18 100644
--- a/src/cpu/o3/fetch_impl.hh
+++ b/src/cpu/o3/fetch_impl.hh
@@ -601,7 +601,8 @@ DefaultFetch<Impl>::fetchCacheLine(Addr fetch_PC, Fault &ret_fault, unsigned tid
     memReq[tid] = mem_req;
 
     // Translate the instruction request.
-    fault = cpu->itb->translateAtomic(mem_req, cpu->thread[tid]->getTC());
+    fault = cpu->itb->translateAtomic(mem_req, cpu->thread[tid]->getTC(),
+            false, true);
 
     // In the case of faults, the fetch stage may need to stall and wait
     // for the ITB miss to be handled.
diff --git a/src/cpu/o3/thread_context.hh b/src/cpu/o3/thread_context.hh
index f3058925d..c402e8fd9 100755
--- a/src/cpu/o3/thread_context.hh
+++ b/src/cpu/o3/thread_context.hh
@@ -67,10 +67,10 @@ class O3ThreadContext : public ThreadContext
     O3ThreadState<Impl> *thread;
 
     /** Returns a pointer to the ITB. */
-    TheISA::ITB *getITBPtr() { return cpu->itb; }
+    TheISA::TLB *getITBPtr() { return cpu->itb; }
 
     /** Returns a pointer to the DTB. */
-    TheISA::DTB *getDTBPtr() { return cpu->dtb; }
+    TheISA::TLB *getDTBPtr() { return cpu->dtb; }
 
     /** Returns a pointer to this CPU. */
     virtual BaseCPU *getCpuPtr() { return cpu; }
diff --git a/src/cpu/ozone/cpu.hh b/src/cpu/ozone/cpu.hh
index 0bfb4bfa9..af62f863a 100644
--- a/src/cpu/ozone/cpu.hh
+++ b/src/cpu/ozone/cpu.hh
@@ -53,8 +53,7 @@
 
 namespace TheISA
 {
-    class ITB;
-    class DTB;
+    class TLB;
 }
 class PhysicalMemory;
 class MemoryController;
@@ -116,9 +115,9 @@ class OzoneCPU : public BaseCPU
 
         BaseCPU *getCpuPtr();
 
-        TheISA::ITB *getITBPtr() { return cpu->itb; }
+        TheISA::TLB *getITBPtr() { return cpu->itb; }
 
-        TheISA::DTB * getDTBPtr() { return cpu->dtb; }
+        TheISA::TLB * getDTBPtr() { return cpu->dtb; }
 
 #if FULL_SYSTEM
         System *getSystemPtr() { return cpu->system; }
@@ -349,8 +348,8 @@ class OzoneCPU : public BaseCPU
 
     bool interval_stats;
 
-    TheISA::ITB *itb;
-    TheISA::DTB *dtb;
+    TheISA::TLB *itb;
+    TheISA::TLB *dtb;
     System *system;
     PhysicalMemory *physmem;
 #endif
diff --git a/src/cpu/ozone/front_end_impl.hh b/src/cpu/ozone/front_end_impl.hh
index 6b47ef539..516823b47 100644
--- a/src/cpu/ozone/front_end_impl.hh
+++ b/src/cpu/ozone/front_end_impl.hh
@@ -480,7 +480,7 @@ FrontEnd<Impl>::fetchCacheLine()
                          PC, cpu->thread->contextId());
 
     // Translate the instruction request.
-    fault = cpu->itb->translateAtomic(memReq, thread);
+    fault = cpu->itb->translateAtomic(memReq, thread, false, true);
 
     // Now do the timing access to see whether or not the instruction
     // exists within the cache.
diff --git a/src/cpu/ozone/simple_params.hh b/src/cpu/ozone/simple_params.hh
index ec5782c8a..7687fdf60 100644
--- a/src/cpu/ozone/simple_params.hh
+++ b/src/cpu/ozone/simple_params.hh
@@ -36,8 +36,7 @@
 //Forward declarations
 namespace TheISA
 {
-    class DTB;
-    class ITB;
+    class TLB;
 }
 class FUPool;
 class MemObject;
@@ -55,7 +54,7 @@ class SimpleParams : public BaseCPU::Params
 {
   public:
 
-    TheISA::ITB *itb; TheISA::DTB *dtb;
+    TheISA::TLB *itb; TheISA::TLB *dtb;
 #if !FULL_SYSTEM
     std::vector<Process *> workload;
 #endif // FULL_SYSTEM
diff --git a/src/cpu/simple/atomic.cc b/src/cpu/simple/atomic.cc
index 17f93c882..b5e65265a 100644
--- a/src/cpu/simple/atomic.cc
+++ b/src/cpu/simple/atomic.cc
@@ -609,7 +609,7 @@ AtomicSimpleCPU::tick()
         bool fromRom = isRomMicroPC(thread->readMicroPC());
         if (!fromRom && !curMacroStaticInst) {
             setupFetchRequest(&ifetch_req);
-            fault = thread->itb->translateAtomic(&ifetch_req, tc);
+            fault = thread->itb->translateAtomic(&ifetch_req, tc, false, true);
         }
 
         if (fault == NoFault) {
diff --git a/src/cpu/simple/timing.cc b/src/cpu/simple/timing.cc
index a8f86f8d2..874eeefb7 100644
--- a/src/cpu/simple/timing.cc
+++ b/src/cpu/simple/timing.cc
@@ -672,7 +672,7 @@ TimingSimpleCPU::fetch()
         ifetch_req->setThreadContext(_cpuId, /* thread ID */ 0);
         setupFetchRequest(ifetch_req);
         thread->itb->translateTiming(ifetch_req, tc,
-                &fetchTranslation);
+                &fetchTranslation, false, true);
     } else {
         _status = IcacheWaitResponse;
         completeIfetch(NULL);
diff --git a/src/cpu/simple/timing.hh b/src/cpu/simple/timing.hh
index a02ec48c9..731eeeefc 100644
--- a/src/cpu/simple/timing.hh
+++ b/src/cpu/simple/timing.hh
@@ -106,7 +106,7 @@ class TimingSimpleCPU : public BaseSimpleCPU
         {}
 
         void finish(Fault fault, RequestPtr req,
-                ThreadContext *tc, bool write)
+                ThreadContext *tc, bool write, bool execute)
         {
             cpu->sendFetch(fault, req, tc);
         }
@@ -129,7 +129,7 @@ class TimingSimpleCPU : public BaseSimpleCPU
 
         void
         finish(Fault fault, RequestPtr req,
-                ThreadContext *tc, bool write)
+                ThreadContext *tc, bool write, bool execute)
         {
             cpu->sendData(fault, req, data, res, read);
             delete this;
@@ -173,7 +173,7 @@ class TimingSimpleCPU : public BaseSimpleCPU
 
         void
         finish(Fault fault, RequestPtr req,
-                ThreadContext *tc, bool write)
+                ThreadContext *tc, bool write, bool execute)
         {
             assert(state);
             assert(state->outstanding);
diff --git a/src/cpu/simple_thread.cc b/src/cpu/simple_thread.cc
index af0bb4490..6ede3f429 100644
--- a/src/cpu/simple_thread.cc
+++ b/src/cpu/simple_thread.cc
@@ -61,7 +61,7 @@ using namespace std;
 // constructor
 #if FULL_SYSTEM
 SimpleThread::SimpleThread(BaseCPU *_cpu, int _thread_num, System *_sys,
-                           TheISA::ITB *_itb, TheISA::DTB *_dtb,
+                           TheISA::TLB *_itb, TheISA::TLB *_dtb,
                            bool use_kernel_stats)
     : ThreadState(_cpu, _thread_num), cpu(_cpu), system(_sys), itb(_itb),
       dtb(_dtb)
@@ -92,7 +92,7 @@ SimpleThread::SimpleThread(BaseCPU *_cpu, int _thread_num, System *_sys,
 }
 #else
 SimpleThread::SimpleThread(BaseCPU *_cpu, int _thread_num, Process *_process,
-                           TheISA::ITB *_itb, TheISA::DTB *_dtb, int _asid)
+                           TheISA::TLB *_itb, TheISA::TLB *_dtb, int _asid)
     : ThreadState(_cpu, _thread_num, _process, _asid),
       cpu(_cpu), itb(_itb), dtb(_dtb)
 {
diff --git a/src/cpu/simple_thread.hh b/src/cpu/simple_thread.hh
index 73929d362..5194a01ec 100644
--- a/src/cpu/simple_thread.hh
+++ b/src/cpu/simple_thread.hh
@@ -108,17 +108,17 @@ class SimpleThread : public ThreadState
 
     System *system;
 
-    TheISA::ITB *itb;
-    TheISA::DTB *dtb;
+    TheISA::TLB *itb;
+    TheISA::TLB *dtb;
 
     // constructor: initialize SimpleThread from given process structure
 #if FULL_SYSTEM
     SimpleThread(BaseCPU *_cpu, int _thread_num, System *_system,
-                 TheISA::ITB *_itb, TheISA::DTB *_dtb,
+                 TheISA::TLB *_itb, TheISA::TLB *_dtb,
                  bool use_kernel_stats = true);
 #else
     SimpleThread(BaseCPU *_cpu, int _thread_num, Process *_process,
-                 TheISA::ITB *_itb, TheISA::DTB *_dtb, int _asid);
+                 TheISA::TLB *_itb, TheISA::TLB *_dtb, int _asid);
 #endif
 
     SimpleThread();
@@ -181,9 +181,9 @@ class SimpleThread : public ThreadState
 
     BaseCPU *getCpuPtr() { return cpu; }
 
-    TheISA::ITB *getITBPtr() { return itb; }
+    TheISA::TLB *getITBPtr() { return itb; }
 
-    TheISA::DTB *getDTBPtr() { return dtb; }
+    TheISA::TLB *getDTBPtr() { return dtb; }
 
     System *getSystemPtr() { return system; }
 
diff --git a/src/cpu/thread_context.hh b/src/cpu/thread_context.hh
index 700f1571e..72c9df33d 100644
--- a/src/cpu/thread_context.hh
+++ b/src/cpu/thread_context.hh
@@ -44,8 +44,7 @@
 // DTB pointers.
 namespace TheISA
 {
-    class DTB;
-    class ITB;
+    class TLB;
 }
 class BaseCPU;
 class EndQuiesceEvent;
@@ -124,9 +123,9 @@ class ThreadContext
 
     virtual void setContextId(int id) = 0;
 
-    virtual TheISA::ITB *getITBPtr() = 0;
+    virtual TheISA::TLB *getITBPtr() = 0;
 
-    virtual TheISA::DTB *getDTBPtr() = 0;
+    virtual TheISA::TLB *getDTBPtr() = 0;
 
     virtual System *getSystemPtr() = 0;
 
@@ -306,9 +305,9 @@ class ProxyThreadContext : public ThreadContext
 
     void setContextId(int id) { actualTC->setContextId(id); }
 
-    TheISA::ITB *getITBPtr() { return actualTC->getITBPtr(); }
+    TheISA::TLB *getITBPtr() { return actualTC->getITBPtr(); }
 
-    TheISA::DTB *getDTBPtr() { return actualTC->getDTBPtr(); }
+    TheISA::TLB *getDTBPtr() { return actualTC->getDTBPtr(); }
 
     System *getSystemPtr() { return actualTC->getSystemPtr(); }