Merge zizzer:/bk/sparcfs

into  zed.eecs.umich.edu:/z/hsul/work/sparc/m5

--HG--
extra : convert_revision : 2f11b5f9fa6356cbf9f98c8cd7d4f6fbfaf9d24d

14 files changed, 153 insertions, 361 deletions

diff --git a/src/cpu/base_dyn_inst.hh b/src/cpu/base_dyn_inst.hh
index 4a4555566..9037c96df 100644
--- a/src/cpu/base_dyn_inst.hh
+++ b/src/cpu/base_dyn_inst.hh
@@ -406,14 +406,15 @@ class BaseDynInst : public FastAlloc, public RefCounted
     double readDoubleResult() { return instResult.dbl; }
 
     /** Records an integer register being set to a value. */
-    void setIntReg(const StaticInst *si, int idx, uint64_t val)
+    void setIntRegOperand(const StaticInst *si, int idx, uint64_t val)
     {
         if (recordResult)
             instResult.integer = val;
     }
 
     /** Records an fp register being set to a value. */
-    void setFloatReg(const StaticInst *si, int idx, FloatReg val, int width)
+    void setFloatRegOperand(const StaticInst *si, int idx, FloatReg val,
+                            int width)
     {
         if (recordResult) {
             if (width == 32)
@@ -426,21 +427,22 @@ class BaseDynInst : public FastAlloc, public RefCounted
     }
 
     /** Records an fp register being set to a value. */
-    void setFloatReg(const StaticInst *si, int idx, FloatReg val)
+    void setFloatRegOperand(const StaticInst *si, int idx, FloatReg val)
     {
         if (recordResult)
             instResult.dbl = (double)val;
     }
 
     /** Records an fp register being set to an integer value. */
-    void setFloatRegBits(const StaticInst *si, int idx, uint64_t val, int width)
+    void setFloatRegOperandBits(const StaticInst *si, int idx, uint64_t val,
+                                int width)
     {
         if (recordResult)
             instResult.integer = val;
     }
 
     /** Records an fp register being set to an integer value. */
-    void setFloatRegBits(const StaticInst *si, int idx, uint64_t val)
+    void setFloatRegOperandBits(const StaticInst *si, int idx, uint64_t val)
     {
         if (recordResult)
             instResult.integer = val;
diff --git a/src/cpu/checker/cpu.hh b/src/cpu/checker/cpu.hh
index 9be54529f..3e08193ee 100644
--- a/src/cpu/checker/cpu.hh
+++ b/src/cpu/checker/cpu.hh
@@ -216,42 +216,44 @@ class CheckerCPU : public BaseCPU
     // storage (which is pretty hard to imagine they would have reason
     // to do).
 
-    uint64_t readIntReg(const StaticInst *si, int idx)
+    uint64_t readIntRegOperand(const StaticInst *si, int idx)
     {
         return thread->readIntReg(si->srcRegIdx(idx));
     }
 
-    FloatReg readFloatReg(const StaticInst *si, int idx, int width)
+    FloatReg readFloatRegOperand(const StaticInst *si, int idx, int width)
     {
         int reg_idx = si->srcRegIdx(idx) - TheISA::FP_Base_DepTag;
         return thread->readFloatReg(reg_idx, width);
     }
 
-    FloatReg readFloatReg(const StaticInst *si, int idx)
+    FloatReg readFloatRegOperand(const StaticInst *si, int idx)
     {
         int reg_idx = si->srcRegIdx(idx) - TheISA::FP_Base_DepTag;
         return thread->readFloatReg(reg_idx);
     }
 
-    FloatRegBits readFloatRegBits(const StaticInst *si, int idx, int width)
+    FloatRegBits readFloatRegOperandBits(const StaticInst *si, int idx,
+                                         int width)
     {
         int reg_idx = si->srcRegIdx(idx) - TheISA::FP_Base_DepTag;
         return thread->readFloatRegBits(reg_idx, width);
     }
 
-    FloatRegBits readFloatRegBits(const StaticInst *si, int idx)
+    FloatRegBits readFloatRegOperandBits(const StaticInst *si, int idx)
     {
         int reg_idx = si->srcRegIdx(idx) - TheISA::FP_Base_DepTag;
         return thread->readFloatRegBits(reg_idx);
     }
 
-    void setIntReg(const StaticInst *si, int idx, uint64_t val)
+    void setIntRegOperand(const StaticInst *si, int idx, uint64_t val)
     {
         thread->setIntReg(si->destRegIdx(idx), val);
         result.integer = val;
     }
 
-    void setFloatReg(const StaticInst *si, int idx, FloatReg val, int width)
+    void setFloatRegOperand(const StaticInst *si, int idx, FloatReg val,
+                            int width)
     {
         int reg_idx = si->destRegIdx(idx) - TheISA::FP_Base_DepTag;
         thread->setFloatReg(reg_idx, val, width);
@@ -265,22 +267,23 @@ class CheckerCPU : public BaseCPU
         };
     }
 
-    void setFloatReg(const StaticInst *si, int idx, FloatReg val)
+    void setFloatRegOperand(const StaticInst *si, int idx, FloatReg val)
     {
         int reg_idx = si->destRegIdx(idx) - TheISA::FP_Base_DepTag;
         thread->setFloatReg(reg_idx, val);
         result.dbl = (double)val;
     }
 
-    void setFloatRegBits(const StaticInst *si, int idx, FloatRegBits val,
-                         int width)
+    void setFloatRegOperandBits(const StaticInst *si, int idx,
+                                FloatRegBits val, int width)
     {
         int reg_idx = si->destRegIdx(idx) - TheISA::FP_Base_DepTag;
         thread->setFloatRegBits(reg_idx, val, width);
         result.integer = val;
     }
 
-    void setFloatRegBits(const StaticInst *si, int idx, FloatRegBits val)
+    void setFloatRegOperandBits(const StaticInst *si, int idx,
+                                FloatRegBits val)
     {
         int reg_idx = si->destRegIdx(idx) - TheISA::FP_Base_DepTag;
         thread->setFloatRegBits(reg_idx, val);
diff --git a/src/cpu/exec_context.hh b/src/cpu/exec_context.hh
index 13f70fa79..edccd747f 100644
--- a/src/cpu/exec_context.hh
+++ b/src/cpu/exec_context.hh
@@ -48,39 +48,42 @@ class ExecContext {
     // to do).
 
     /** Reads an integer register. */
-    uint64_t readIntReg(const StaticInst *si, int idx);
+    uint64_t readIntRegOperand(const StaticInst *si, int idx);
 
     /** Reads a floating point register of a specific width. */
-    FloatReg readFloatReg(const StaticInst *si, int idx, int width);
+    FloatReg readFloatRegOperand(const StaticInst *si, int idx, int width);
 
     /** Reads a floating point register of single register width. */
-    FloatReg readFloatReg(const StaticInst *si, int idx);
+    FloatReg readFloatRegOperand(const StaticInst *si, int idx);
 
     /** Reads a floating point register of a specific width in its
      * binary format, instead of by value. */
-    FloatRegBits readFloatRegBits(const StaticInst *si, int idx, int width);
+    FloatRegBits readFloatRegOperandBits(const StaticInst *si, int idx,
+                                         int width);
 
     /** Reads a floating point register in its binary format, instead
      * of by value. */
-    FloatRegBits readFloatRegBits(const StaticInst *si, int idx);
+    FloatRegBits readFloatRegOperandBits(const StaticInst *si, int idx);
 
     /** Sets an integer register to a value. */
-    void setIntReg(const StaticInst *si, int idx, uint64_t val);
+    void setIntRegOperand(const StaticInst *si, int idx, uint64_t val);
 
     /** Sets a floating point register of a specific width to a value. */
-    void setFloatReg(const StaticInst *si, int idx, FloatReg val, int width);
+    void setFloatRegOperand(const StaticInst *si, int idx, FloatReg val,
+                            int width);
 
     /** Sets a floating point register of single width to a value. */
-    void setFloatReg(const StaticInst *si, int idx, FloatReg val);
+    void setFloatRegOperand(const StaticInst *si, int idx, FloatReg val);
 
     /** Sets the bits of a floating point register of a specific width
      * to a binary value. */
-    void setFloatRegBits(const StaticInst *si, int idx,
-                         FloatRegBits val, int width);
+    void setFloatRegOperandBits(const StaticInst *si, int idx,
+                                FloatRegBits val, int width);
 
     /** Sets the bits of a floating point register of single width
      * to a binary value. */
-    void setFloatRegBits(const StaticInst *si, int idx, FloatRegBits val);
+    void setFloatRegOperandBits(const StaticInst *si, int idx,
+                                FloatRegBits val);
 
     /** Reads the PC. */
     uint64_t readPC();
diff --git a/src/cpu/o3/alpha/dyn_inst.hh b/src/cpu/o3/alpha/dyn_inst.hh
index 31df8ff78..49cc5a201 100644
--- a/src/cpu/o3/alpha/dyn_inst.hh
+++ b/src/cpu/o3/alpha/dyn_inst.hh
@@ -163,27 +163,28 @@ class AlphaDynInst : public BaseDynInst<Impl>
     // storage (which is pretty hard to imagine they would have reason
     // to do).
 
-    uint64_t readIntReg(const StaticInst *si, int idx)
+    uint64_t readIntRegOperand(const StaticInst *si, int idx)
     {
         return this->cpu->readIntReg(_srcRegIdx[idx]);
     }
 
-    FloatReg readFloatReg(const StaticInst *si, int idx, int width)
+    FloatReg readFloatRegOperand(const StaticInst *si, int idx, int width)
     {
         return this->cpu->readFloatReg(_srcRegIdx[idx], width);
     }
 
-    FloatReg readFloatReg(const StaticInst *si, int idx)
+    FloatReg readFloatRegOperand(const StaticInst *si, int idx)
     {
         return this->cpu->readFloatReg(_srcRegIdx[idx]);
     }
 
-    FloatRegBits readFloatRegBits(const StaticInst *si, int idx, int width)
+    FloatRegBits readFloatRegOperandBits(const StaticInst *si, int idx,
+                                         int width)
     {
         return this->cpu->readFloatRegBits(_srcRegIdx[idx], width);
     }
 
-    FloatRegBits readFloatRegBits(const StaticInst *si, int idx)
+    FloatRegBits readFloatRegOperandBits(const StaticInst *si, int idx)
     {
         return this->cpu->readFloatRegBits(_srcRegIdx[idx]);
     }
@@ -191,35 +192,37 @@ class AlphaDynInst : public BaseDynInst<Impl>
     /** @todo: Make results into arrays so they can handle multiple dest
      *  registers.
      */
-    void setIntReg(const StaticInst *si, int idx, uint64_t val)
+    void setIntRegOperand(const StaticInst *si, int idx, uint64_t val)
     {
         this->cpu->setIntReg(_destRegIdx[idx], val);
-        BaseDynInst<Impl>::setIntReg(si, idx, val);
+        BaseDynInst<Impl>::setIntRegOperand(si, idx, val);
     }
 
-    void setFloatReg(const StaticInst *si, int idx, FloatReg val, int width)
+    void setFloatRegOperand(const StaticInst *si, int idx, FloatReg val,
+                            int width)
     {
         this->cpu->setFloatReg(_destRegIdx[idx], val, width);
-        BaseDynInst<Impl>::setFloatReg(si, idx, val, width);
+        BaseDynInst<Impl>::setFloatRegOperand(si, idx, val, width);
     }
 
-    void setFloatReg(const StaticInst *si, int idx, FloatReg val)
+    void setFloatRegOperand(const StaticInst *si, int idx, FloatReg val)
     {
         this->cpu->setFloatReg(_destRegIdx[idx], val);
-        BaseDynInst<Impl>::setFloatReg(si, idx, val);
+        BaseDynInst<Impl>::setFloatRegOperand(si, idx, val);
     }
 
-    void setFloatRegBits(const StaticInst *si, int idx,
-            FloatRegBits val, int width)
+    void setFloatRegOperandBits(const StaticInst *si, int idx,
+                                FloatRegBits val, int width)
     {
         this->cpu->setFloatRegBits(_destRegIdx[idx], val, width);
-        BaseDynInst<Impl>::setFloatRegBits(si, idx, val);
+        BaseDynInst<Impl>::setFloatRegOperandBits(si, idx, val);
     }
 
-    void setFloatRegBits(const StaticInst *si, int idx, FloatRegBits val)
+    void setFloatRegOperandBits(const StaticInst *si, int idx,
+                                FloatRegBits val)
     {
         this->cpu->setFloatRegBits(_destRegIdx[idx], val);
-        BaseDynInst<Impl>::setFloatRegBits(si, idx, val);
+        BaseDynInst<Impl>::setFloatRegOperandBits(si, idx, val);
     }
 
     /** Returns the physical register index of the i'th destination
diff --git a/src/cpu/o3/commit_impl.hh b/src/cpu/o3/commit_impl.hh
index e72679710..f400d757b 100644
--- a/src/cpu/o3/commit_impl.hh
+++ b/src/cpu/o3/commit_impl.hh
@@ -748,6 +748,7 @@ DefaultCommit<Impl>::commit()
                 }
             } else {
                 bdelay_done_seq_num = squashed_inst;
+                squash_bdelay_slot = true;
             }
 #endif
 
@@ -1196,16 +1197,16 @@ DefaultCommit<Impl>::getInsts()
              rename_idx < fromRename->size;
              rename_idx++) {
             DynInstPtr inst = fromRename->insts[rename_idx];
-            int tid = inst->threadNumber;
 
             if (!inst->isSquashed()) {
                 DPRINTF(Commit, "Inserting PC %#x [sn:%i] [tid:%i] into ",
-                        "skidBuffer.\n", inst->readPC(), inst->seqNum, tid);
+                        "skidBuffer.\n", inst->readPC(), inst->seqNum,
+                        inst->threadNumber);
                 skidBuffer.push(inst);
             } else {
                 DPRINTF(Commit, "Instruction PC %#x [sn:%i] [tid:%i] was "
                         "squashed, skipping.\n",
-                        inst->readPC(), inst->seqNum, tid);
+                        inst->readPC(), inst->seqNum, inst->threadNumber);
             }
         }
     }
diff --git a/src/cpu/o3/fetch_impl.hh b/src/cpu/o3/fetch_impl.hh
index 63d22b293..622259495 100644
--- a/src/cpu/o3/fetch_impl.hh
+++ b/src/cpu/o3/fetch_impl.hh
@@ -151,36 +151,6 @@ DefaultFetch<Impl>::DefaultFetch(Params *params)
               " RoundRobin,LSQcount,IQcount}\n");
     }
 
-    // Size of cache block.
-    cacheBlkSize = 64;
-
-    // Create mask to get rid of offset bits.
-    cacheBlkMask = (cacheBlkSize - 1);
-
-    for (int tid=0; tid < numThreads; tid++) {
-
-        fetchStatus[tid] = Running;
-
-        priorityList.push_back(tid);
-
-        memReq[tid] = NULL;
-
-        // Create space to store a cache line.
-        cacheData[tid] = new uint8_t[cacheBlkSize];
-        cacheDataPC[tid] = 0;
-        cacheDataValid[tid] = false;
-
-        delaySlotInfo[tid].branchSeqNum = -1;
-        delaySlotInfo[tid].numInsts = 0;
-        delaySlotInfo[tid].targetAddr = 0;
-        delaySlotInfo[tid].targetReady = false;
-
-        stalls[tid].decode = false;
-        stalls[tid].rename = false;
-        stalls[tid].iew = false;
-        stalls[tid].commit = false;
-    }
-
     // Get the size of an instruction.
     instSize = sizeof(TheISA::MachInst);
 }
@@ -353,6 +323,36 @@ DefaultFetch<Impl>::initStage()
         nextNPC[tid] = cpu->readNextNPC(tid);
 #endif
     }
+
+    // Size of cache block.
+    cacheBlkSize = icachePort->peerBlockSize();
+
+    // Create mask to get rid of offset bits.
+    cacheBlkMask = (cacheBlkSize - 1);
+
+    for (int tid=0; tid < numThreads; tid++) {
+
+        fetchStatus[tid] = Running;
+
+        priorityList.push_back(tid);
+
+        memReq[tid] = NULL;
+
+        // Create space to store a cache line.
+        cacheData[tid] = new uint8_t[cacheBlkSize];
+        cacheDataPC[tid] = 0;
+        cacheDataValid[tid] = false;
+
+        delaySlotInfo[tid].branchSeqNum = -1;
+        delaySlotInfo[tid].numInsts = 0;
+        delaySlotInfo[tid].targetAddr = 0;
+        delaySlotInfo[tid].targetReady = false;
+
+        stalls[tid].decode = false;
+        stalls[tid].rename = false;
+        stalls[tid].iew = false;
+        stalls[tid].commit = false;
+    }
 }
 
 template<class Impl>
@@ -1139,6 +1139,8 @@ DefaultFetch<Impl>::fetch(bool &status_change)
             ext_inst = TheISA::makeExtMI(inst, fetch_PC);
 #elif THE_ISA == SPARC_ISA
             ext_inst = TheISA::makeExtMI(inst, cpu->thread[tid]->getTC());
+#elif THE_ISA == MIPS_ISA
+            ext_inst = TheISA::makeExtMI(inst, cpu->thread[tid]->getTC());
 #endif
 
             // Create a new DynInst from the instruction fetched.
diff --git a/src/cpu/o3/iew_impl.hh b/src/cpu/o3/iew_impl.hh
index ba5260fe2..76047b295 100644
--- a/src/cpu/o3/iew_impl.hh
+++ b/src/cpu/o3/iew_impl.hh
@@ -514,6 +514,7 @@ DefaultIEW<Impl>::squashDueToMemOrder(DynInstPtr &inst, unsigned tid)
     toCommit->squash[tid] = true;
     toCommit->squashedSeqNum[tid] = inst->seqNum;
     toCommit->nextPC[tid] = inst->readNextPC();
+    toCommit->branchMispredict[tid] = false;
 
     toCommit->includeSquashInst[tid] = false;
 
@@ -530,6 +531,7 @@ DefaultIEW<Impl>::squashDueToMemBlocked(DynInstPtr &inst, unsigned tid)
     toCommit->squash[tid] = true;
     toCommit->squashedSeqNum[tid] = inst->seqNum;
     toCommit->nextPC[tid] = inst->readPC();
+    toCommit->branchMispredict[tid] = false;
 
     // Must include the broadcasted SN in the squash.
     toCommit->includeSquashInst[tid] = true;
@@ -1291,7 +1293,8 @@ DefaultIEW<Impl>::executeInsts()
                 } else if (fault != NoFault) {
                     // If the instruction faulted, then we need to send it along to commit
                     // without the instruction completing.
-                    DPRINTF(IEW, "Store has fault! [sn:%lli]\n", inst->seqNum);
+                    DPRINTF(IEW, "Store has fault %s! [sn:%lli]\n",
+                            fault->name(), inst->seqNum);
 
                     // Send this instruction to commit, also make sure iew stage
                     // realizes there is activity.
@@ -1328,7 +1331,8 @@ DefaultIEW<Impl>::executeInsts()
         // instruction first, so the branch resolution order will be correct.
         unsigned tid = inst->threadNumber;
 
-        if (!fetchRedirect[tid]) {
+        if (!fetchRedirect[tid] ||
+            toCommit->squashedSeqNum[tid] > inst->seqNum) {
 
             if (inst->mispredicted()) {
                 fetchRedirect[tid] = true;
@@ -1350,8 +1354,6 @@ DefaultIEW<Impl>::executeInsts()
                     predictedNotTakenIncorrect++;
                 }
             } else if (ldstQueue.violation(tid)) {
-                fetchRedirect[tid] = true;
-
                 // If there was an ordering violation, then get the
                 // DynInst that caused the violation.  Note that this
                 // clears the violation signal.
@@ -1362,6 +1364,14 @@ DefaultIEW<Impl>::executeInsts()
                         "%#x, inst PC: %#x.  Addr is: %#x.\n",
                         violator->readPC(), inst->readPC(), inst->physEffAddr);
 
+                // Ensure the violating instruction is older than
+                // current squash
+                if (fetchRedirect[tid] &&
+                    violator->seqNum >= toCommit->squashedSeqNum[tid])
+                    continue;
+
+                fetchRedirect[tid] = true;
+
                 // Tell the instruction queue that a violation has occured.
                 instQueue.violation(inst, violator);
 
diff --git a/src/cpu/o3/lsq_unit_impl.hh b/src/cpu/o3/lsq_unit_impl.hh
index 4facea9f9..3b84d3411 100644
--- a/src/cpu/o3/lsq_unit_impl.hh
+++ b/src/cpu/o3/lsq_unit_impl.hh
@@ -418,7 +418,8 @@ LSQUnit<Impl>::executeLoad(DynInstPtr &inst)
         // realizes there is activity.
         // Mark it as executed unless it is an uncached load that
         // needs to hit the head of commit.
-        if (!(inst->req->isUncacheable()) || inst->isAtCommit()) {
+        if (!(inst->req && inst->req->isUncacheable()) ||
+            inst->isAtCommit()) {
             inst->setExecuted();
         }
         iewStage->instToCommit(inst);
diff --git a/src/cpu/o3/mips/dyn_inst.hh b/src/cpu/o3/mips/dyn_inst.hh
index 9e95b2bfb..833371e00 100755
--- a/src/cpu/o3/mips/dyn_inst.hh
+++ b/src/cpu/o3/mips/dyn_inst.hh
@@ -156,27 +156,28 @@ class MipsDynInst : public BaseDynInst<Impl>
     // storage (which is pretty hard to imagine they would have reason
     // to do).
 
-    uint64_t readIntReg(const StaticInst *si, int idx)
+    uint64_t readIntRegOperand(const StaticInst *si, int idx)
     {
         return this->cpu->readIntReg(_srcRegIdx[idx]);
     }
 
-    FloatReg readFloatReg(const StaticInst *si, int idx, int width)
+    FloatReg readFloatRegOperand(const StaticInst *si, int idx, int width)
     {
         return this->cpu->readFloatReg(_srcRegIdx[idx], width);
     }
 
-    FloatReg readFloatReg(const StaticInst *si, int idx)
+    FloatReg readFloatRegOperand(const StaticInst *si, int idx)
     {
         return this->cpu->readFloatReg(_srcRegIdx[idx]);
     }
 
-    FloatRegBits readFloatRegBits(const StaticInst *si, int idx, int width)
+    FloatRegBits readFloatRegOperandBits(const StaticInst *si, int idx,
+                                         int width)
     {
         return this->cpu->readFloatRegBits(_srcRegIdx[idx], width);
     }
 
-    FloatRegBits readFloatRegBits(const StaticInst *si, int idx)
+    FloatRegBits readFloatRegOperandBits(const StaticInst *si, int idx)
     {
         return this->cpu->readFloatRegBits(_srcRegIdx[idx]);
     }
@@ -184,35 +185,37 @@ class MipsDynInst : public BaseDynInst<Impl>
     /** @todo: Make results into arrays so they can handle multiple dest
      *  registers.
      */
-    void setIntReg(const StaticInst *si, int idx, uint64_t val)
+    void setIntRegOperand(const StaticInst *si, int idx, uint64_t val)
     {
         this->cpu->setIntReg(_destRegIdx[idx], val);
-        BaseDynInst<Impl>::setIntReg(si, idx, val);
+        BaseDynInst<Impl>::setIntRegOperand(si, idx, val);
     }
 
-    void setFloatReg(const StaticInst *si, int idx, FloatReg val, int width)
+    void setFloatRegOperand(const StaticInst *si, int idx, FloatReg val,
+                            int width)
     {
         this->cpu->setFloatReg(_destRegIdx[idx], val, width);
-        BaseDynInst<Impl>::setFloatReg(si, idx, val, width);
+        BaseDynInst<Impl>::setFloatRegOperand(si, idx, val, width);
     }
 
-    void setFloatReg(const StaticInst *si, int idx, FloatReg val)
+    void setFloatRegOperand(const StaticInst *si, int idx, FloatReg val)
     {
         this->cpu->setFloatReg(_destRegIdx[idx], val);
-        BaseDynInst<Impl>::setFloatReg(si, idx, val);
+        BaseDynInst<Impl>::setFloatRegOperand(si, idx, val);
     }
 
-    void setFloatRegBits(const StaticInst *si, int idx,
-            FloatRegBits val, int width)
+    void setFloatRegOperandBits(const StaticInst *si, int idx,
+                                FloatRegBits val, int width)
     {
         this->cpu->setFloatRegBits(_destRegIdx[idx], val, width);
-        BaseDynInst<Impl>::setFloatRegBits(si, idx, val);
+        BaseDynInst<Impl>::setFloatRegOperandBits(si, idx, val);
     }
 
-    void setFloatRegBits(const StaticInst *si, int idx, FloatRegBits val)
+    void setFloatRegOperandBits(const StaticInst *si, int idx,
+                                FloatRegBits val)
     {
         this->cpu->setFloatRegBits(_destRegIdx[idx], val);
-        BaseDynInst<Impl>::setFloatRegBits(si, idx, val);
+        BaseDynInst<Impl>::setFloatRegOperandBits(si, idx, val);
     }
 
     /** Returns the physical register index of the i'th destination
diff --git a/src/cpu/ozone/cpu.hh b/src/cpu/ozone/cpu.hh
index c1373944d..0da446c9c 100644
--- a/src/cpu/ozone/cpu.hh
+++ b/src/cpu/ozone/cpu.hh
@@ -448,30 +448,6 @@ class OzoneCPU : public BaseCPU
     }
 #endif
 
-    /** Old CPU read from memory function. No longer used. */
-    template <class T>
-    Fault read(Request *req, T &data)
-    {
-#if 0
-#if FULL_SYSTEM && defined(TARGET_ALPHA)
-        if (req->isLocked()) {
-            req->xc->setMiscReg(TheISA::Lock_Addr_DepTag, req->paddr);
-            req->xc->setMiscReg(TheISA::Lock_Flag_DepTag, true);
-        }
-#endif
-        if (req->isLocked()) {
-            lockAddrList.insert(req->paddr);
-            lockFlag = true;
-        }
-#endif
-        Fault error;
-
-        error = this->mem->read(req, data);
-        data = gtoh(data);
-        return error;
-    }
-
-
     /** CPU read function, forwards read to LSQ. */
     template <class T>
     Fault read(Request *req, T &data, int load_idx)
@@ -479,81 +455,6 @@ class OzoneCPU : public BaseCPU
         return backEnd->read(req, data, load_idx);
     }
 
-    /** Old CPU write to memory function. No longer used. */
-    template <class T>
-    Fault write(Request *req, T &data)
-    {
-#if 0
-#if FULL_SYSTEM && defined(TARGET_ALPHA)
-        ExecContext *xc;
-
-        // If this is a store conditional, act appropriately
-        if (req->isLocked()) {
-            xc = req->xc;
-
-            if (req->isUncacheable()) {
-                // Don't update result register (see stq_c in isa_desc)
-                req->result = 2;
-                xc->setStCondFailures(0);//Needed? [RGD]
-            } else {
-                bool lock_flag = xc->readMiscReg(TheISA::Lock_Flag_DepTag);
-                Addr lock_addr = xc->readMiscReg(TheISA::Lock_Addr_DepTag);
-                req->result = lock_flag;
-                if (!lock_flag ||
-                    ((lock_addr & ~0xf) != (req->paddr & ~0xf))) {
-                    xc->setMiscReg(TheISA::Lock_Flag_DepTag, false);
-                    xc->setStCondFailures(xc->readStCondFailures() + 1);
-                    if (((xc->readStCondFailures()) % 100000) == 0) {
-                        std::cerr << "Warning: "
-                                  << xc->readStCondFailures()
-                                  << " consecutive store conditional failures "
-                                  << "on cpu " << req->xc->readCpuId()
-                                  << std::endl;
-                    }
-                    return NoFault;
-                }
-                else xc->setStCondFailures(0);
-            }
-        }
-
-        // Need to clear any locked flags on other proccessors for
-        // this address.  Only do this for succsful Store Conditionals
-        // and all other stores (WH64?).  Unsuccessful Store
-        // Conditionals would have returned above, and wouldn't fall
-        // through.
-        for (int i = 0; i < this->system->threadContexts.size(); i++){
-            xc = this->system->threadContexts[i];
-            if ((xc->readMiscReg(TheISA::Lock_Addr_DepTag) & ~0xf) ==
-                (req->paddr & ~0xf)) {
-                xc->setMiscReg(TheISA::Lock_Flag_DepTag, false);
-            }
-        }
-
-#endif
-
-        if (req->isLocked()) {
-            if (req->isUncacheable()) {
-                req->result = 2;
-            } else {
-                if (this->lockFlag) {
-                    if (lockAddrList.find(req->paddr) !=
-                        lockAddrList.end()) {
-                        req->result = 1;
-                    } else {
-                        req->result = 0;
-                        return NoFault;
-                    }
-                } else {
-                    req->result = 0;
-                    return NoFault;
-                }
-            }
-        }
-#endif
-
-        return this->mem->write(req, (T)htog(data));
-    }
-
     /** CPU write function, forwards write to LSQ. */
     template <class T>
     Fault write(Request *req, T &data, int store_idx)
diff --git a/src/cpu/ozone/dyn_inst.hh b/src/cpu/ozone/dyn_inst.hh
index 9445a5309..88f96b14b 100644
--- a/src/cpu/ozone/dyn_inst.hh
+++ b/src/cpu/ozone/dyn_inst.hh
@@ -146,12 +146,12 @@ class OzoneDynInst : public BaseDynInst<Impl>
     // storage (which is pretty hard to imagine they would have reason
     // to do).
 
-    uint64_t readIntReg(const StaticInst *si, int idx)
+    uint64_t readIntRegOperand(const StaticInst *si, int idx)
     {
         return srcInsts[idx]->readIntResult();
     }
 
-    FloatReg readFloatReg(const StaticInst *si, int idx, int width)
+    FloatReg readFloatRegOperand(const StaticInst *si, int idx, int width)
     {
         switch(width) {
           case 32:
@@ -164,17 +164,18 @@ class OzoneDynInst : public BaseDynInst<Impl>
         }
     }
 
-    FloatReg readFloatReg(const StaticInst *si, int idx)
+    FloatReg readFloatRegOperand(const StaticInst *si, int idx)
     {
         return srcInsts[idx]->readFloatResult();
     }
 
-    FloatRegBits readFloatRegBits(const StaticInst *si, int idx, int width)
+    FloatRegBits readFloatRegOperandBits(const StaticInst *si, int idx,
+                                         int width)
     {
         return srcInsts[idx]->readIntResult();
     }
 
-    FloatRegBits readFloatRegBits(const StaticInst *si, int idx)
+    FloatRegBits readFloatRegOperandBits(const StaticInst *si, int idx)
     {
         return srcInsts[idx]->readIntResult();
     }
@@ -182,28 +183,30 @@ class OzoneDynInst : public BaseDynInst<Impl>
     /** @todo: Make results into arrays so they can handle multiple dest
      *  registers.
      */
-    void setIntReg(const StaticInst *si, int idx, uint64_t val)
+    void setIntRegOperand(const StaticInst *si, int idx, uint64_t val)
     {
         BaseDynInst<Impl>::setIntReg(si, idx, val);
     }
 
-    void setFloatReg(const StaticInst *si, int idx, FloatReg val, int width)
+    void setFloatRegOperand(const StaticInst *si, int idx, FloatReg val,
+                            int width)
     {
         BaseDynInst<Impl>::setFloatReg(si, idx, val, width);
     }
 
-    void setFloatReg(const StaticInst *si, int idx, FloatReg val)
+    void setFloatRegOperand(const StaticInst *si, int idx, FloatReg val)
     {
         BaseDynInst<Impl>::setFloatReg(si, idx, val);
     }
 
-    void setFloatRegBits(const StaticInst *si, int idx,
-            FloatRegBits val, int width)
+    void setFloatRegOperandBits(const StaticInst *si, int idx,
+                                FloatRegBits val, int width)
     {
         BaseDynInst<Impl>::setFloatRegBits(si, idx, val);
     }
 
-    void setFloatRegBits(const StaticInst *si, int idx, FloatRegBits val)
+    void setFloatRegOperandBits(const StaticInst *si, int idx,
+                                FloatRegBits val)
     {
         BaseDynInst<Impl>::setFloatRegBits(si, idx, val);
     }
diff --git a/src/cpu/ozone/inorder_back_end.hh b/src/cpu/ozone/inorder_back_end.hh
index b2522bdc8..4fd8e02f8 100644
--- a/src/cpu/ozone/inorder_back_end.hh
+++ b/src/cpu/ozone/inorder_back_end.hh
@@ -236,25 +236,6 @@ InorderBackEnd<Impl>::read(Addr addr, T &data, unsigned flags)
 */
     return fault;
 }
-#if 0
-template <class Impl>
-template <class T>
-Fault
-InorderBackEnd<Impl>::read(MemReqPtr &req, T &data)
-{
-#if FULL_SYSTEM && defined(TARGET_ALPHA)
-    if (req->isLocked()) {
-        req->xc->setMiscReg(TheISA::Lock_Addr_DepTag, req->paddr);
-        req->xc->setMiscReg(TheISA::Lock_Flag_DepTag, true);
-    }
-#endif
-
-    Fault error;
-    error = thread->mem->read(req, data);
-    data = LittleEndianGuest::gtoh(data);
-    return error;
-}
-#endif
 
 template <class Impl>
 template <class T>
@@ -296,61 +277,6 @@ InorderBackEnd<Impl>::write(T data, Addr addr, unsigned flags, uint64_t *res)
 */
     return fault;
 }
-#if 0
-template <class Impl>
-template <class T>
-Fault
-InorderBackEnd<Impl>::write(MemReqPtr &req, T &data)
-{
-#if FULL_SYSTEM && defined(TARGET_ALPHA)
-    ExecContext *xc;
-
-    // If this is a store conditional, act appropriately
-    if (req->isLocked()) {
-        xc = req->xc;
-
-        if (req->isUncacheable()) {
-            // Don't update result register (see stq_c in isa_desc)
-            req->result = 2;
-            xc->setStCondFailures(0);//Needed? [RGD]
-        } else {
-            bool lock_flag = xc->readMiscReg(TheISA::Lock_Flag_DepTag);
-            Addr lock_addr = xc->readMiscReg(TheISA::Lock_Addr_DepTag);
-            req->result = lock_flag;
-            if (!lock_flag ||
-                ((lock_addr & ~0xf) != (req->paddr & ~0xf))) {
-                xc->setMiscReg(TheISA::Lock_Flag_DepTag, false);
-                xc->setStCondFailures(xc->readStCondFailures() + 1);
-                if (((xc->readStCondFailures()) % 100000) == 0) {
-                    std::cerr << "Warning: "
-                              << xc->readStCondFailures()
-                              << " consecutive store conditional failures "
-                              << "on cpu " << req->xc->readCpuId()
-                              << std::endl;
-                }
-                return NoFault;
-            }
-            else xc->setStCondFailures(0);
-        }
-    }
-
-    // Need to clear any locked flags on other proccessors for
-    // this address.  Only do this for succsful Store Conditionals
-    // and all other stores (WH64?).  Unsuccessful Store
-    // Conditionals would have returned above, and wouldn't fall
-    // through.
-    for (int i = 0; i < cpu->system->execContexts.size(); i++){
-        xc = cpu->system->execContexts[i];
-        if ((xc->readMiscReg(TheISA::Lock_Addr_DepTag) & ~0xf) ==
-            (req->paddr & ~0xf)) {
-            xc->setMiscReg(TheISA::Lock_Flag_DepTag, false);
-        }
-    }
-
-#endif
-    return thread->mem->write(req, (T)LittleEndianGuest::htog(data));
-}
-#endif
 
 template <class Impl>
 template <class T>
diff --git a/src/cpu/simple/base.hh b/src/cpu/simple/base.hh
index efb884325..c39bfa9cd 100644
--- a/src/cpu/simple/base.hh
+++ b/src/cpu/simple/base.hh
@@ -213,60 +213,63 @@ class BaseSimpleCPU : public BaseCPU
     // storage (which is pretty hard to imagine they would have reason
     // to do).
 
-    uint64_t readIntReg(const StaticInst *si, int idx)
+    uint64_t readIntRegOperand(const StaticInst *si, int idx)
     {
         return thread->readIntReg(si->srcRegIdx(idx));
     }
 
-    FloatReg readFloatReg(const StaticInst *si, int idx, int width)
+    FloatReg readFloatRegOperand(const StaticInst *si, int idx, int width)
     {
         int reg_idx = si->srcRegIdx(idx) - TheISA::FP_Base_DepTag;
         return thread->readFloatReg(reg_idx, width);
     }
 
-    FloatReg readFloatReg(const StaticInst *si, int idx)
+    FloatReg readFloatRegOperand(const StaticInst *si, int idx)
     {
         int reg_idx = si->srcRegIdx(idx) - TheISA::FP_Base_DepTag;
         return thread->readFloatReg(reg_idx);
     }
 
-    FloatRegBits readFloatRegBits(const StaticInst *si, int idx, int width)
+    FloatRegBits readFloatRegOperandBits(const StaticInst *si, int idx,
+                                         int width)
     {
         int reg_idx = si->srcRegIdx(idx) - TheISA::FP_Base_DepTag;
         return thread->readFloatRegBits(reg_idx, width);
     }
 
-    FloatRegBits readFloatRegBits(const StaticInst *si, int idx)
+    FloatRegBits readFloatRegOperandBits(const StaticInst *si, int idx)
     {
         int reg_idx = si->srcRegIdx(idx) - TheISA::FP_Base_DepTag;
         return thread->readFloatRegBits(reg_idx);
     }
 
-    void setIntReg(const StaticInst *si, int idx, uint64_t val)
+    void setIntRegOperand(const StaticInst *si, int idx, uint64_t val)
     {
         thread->setIntReg(si->destRegIdx(idx), val);
     }
 
-    void setFloatReg(const StaticInst *si, int idx, FloatReg val, int width)
+    void setFloatRegOperand(const StaticInst *si, int idx, FloatReg val,
+                            int width)
     {
         int reg_idx = si->destRegIdx(idx) - TheISA::FP_Base_DepTag;
         thread->setFloatReg(reg_idx, val, width);
     }
 
-    void setFloatReg(const StaticInst *si, int idx, FloatReg val)
+    void setFloatRegOperand(const StaticInst *si, int idx, FloatReg val)
     {
         int reg_idx = si->destRegIdx(idx) - TheISA::FP_Base_DepTag;
         thread->setFloatReg(reg_idx, val);
     }
 
-    void setFloatRegBits(const StaticInst *si, int idx,
-                         FloatRegBits val, int width)
+    void setFloatRegOperandBits(const StaticInst *si, int idx,
+                                FloatRegBits val, int width)
     {
         int reg_idx = si->destRegIdx(idx) - TheISA::FP_Base_DepTag;
         thread->setFloatRegBits(reg_idx, val, width);
     }
 
-    void setFloatRegBits(const StaticInst *si, int idx, FloatRegBits val)
+    void setFloatRegOperandBits(const StaticInst *si, int idx,
+                                FloatRegBits val)
     {
         int reg_idx = si->destRegIdx(idx) - TheISA::FP_Base_DepTag;
         thread->setFloatRegBits(reg_idx, val);
diff --git a/src/cpu/simple_thread.hh b/src/cpu/simple_thread.hh
index e8757c8c2..10bbe292c 100644
--- a/src/cpu/simple_thread.hh
+++ b/src/cpu/simple_thread.hh
@@ -232,75 +232,6 @@ class SimpleThread : public ThreadState
     /// Set the status to Halted.
     void halt();
 
-/*
-    template <class T>
-    Fault read(RequestPtr &req, T &data)
-    {
-#if FULL_SYSTEM && THE_ISA == ALPHA_ISA
-        if (req->isLocked()) {
-            req->xc->setMiscReg(TheISA::Lock_Addr_DepTag, req->paddr);
-            req->xc->setMiscReg(TheISA::Lock_Flag_DepTag, true);
-        }
-#endif
-
-        Fault error;
-        error = mem->prot_read(req->paddr, data, req->size);
-        data = LittleEndianGuest::gtoh(data);
-        return error;
-    }
-
-    template <class T>
-    Fault write(RequestPtr &req, T &data)
-    {
-#if FULL_SYSTEM && THE_ISA == ALPHA_ISA
-        ExecContext *xc;
-
-        // If this is a store conditional, act appropriately
-        if (req->isLocked()) {
-            xc = req->xc;
-
-            if (req->isUncacheable()) {
-                // Don't update result register (see stq_c in isa_desc)
-                req->result = 2;
-                xc->setStCondFailures(0);//Needed? [RGD]
-            } else {
-                bool lock_flag = xc->readMiscReg(TheISA::Lock_Flag_DepTag);
-                Addr lock_addr = xc->readMiscReg(TheISA::Lock_Addr_DepTag);
-                req->result = lock_flag;
-                if (!lock_flag ||
-                    ((lock_addr & ~0xf) != (req->paddr & ~0xf))) {
-                    xc->setMiscReg(TheISA::Lock_Flag_DepTag, false);
-                    xc->setStCondFailures(xc->readStCondFailures() + 1);
-                    if (((xc->readStCondFailures()) % 100000) == 0) {
-                        std::cerr << "Warning: "
-                                  << xc->readStCondFailures()
-                                  << " consecutive store conditional failures "
-                                  << "on cpu " << req->xc->readCpuId()
-                                  << std::endl;
-                    }
-                    return NoFault;
-                }
-                else xc->setStCondFailures(0);
-            }
-        }
-
-        // Need to clear any locked flags on other proccessors for
-        // this address.  Only do this for succsful Store Conditionals
-        // and all other stores (WH64?).  Unsuccessful Store
-        // Conditionals would have returned above, and wouldn't fall
-        // through.
-        for (int i = 0; i < system->execContexts.size(); i++){
-            xc = system->execContexts[i];
-            if ((xc->readMiscReg(TheISA::Lock_Addr_DepTag) & ~0xf) ==
-                (req->paddr & ~0xf)) {
-                xc->setMiscReg(TheISA::Lock_Flag_DepTag, false);
-            }
-        }
-
-#endif
-        return mem->prot_write(req->paddr, (T)htog(data), req->size);
-    }
-*/
     virtual bool misspeculating();
 
     Fault instRead(RequestPtr &req)