summaryrefslogtreecommitdiff
path: root/src/cpu
diff options
context:
space:
mode:
authorAli Saidi <Ali.Saidi@ARM.com>2012-09-25 11:49:40 -0500
committerAli Saidi <Ali.Saidi@ARM.com>2012-09-25 11:49:40 -0500
commit0c99d21ad748371e801508a8c3652e07e2e56f93 (patch)
treea2a52170a8a88ce919cecb4309428999e5380cfd /src/cpu
parent29acf859ebde2cf219ae636f60d8a46db7a1bb94 (diff)
downloadgem5-0c99d21ad748371e801508a8c3652e07e2e56f93.tar.xz
ARM: Squash outstanding walks when instructions are squashed.
Diffstat (limited to 'src/cpu')
-rw-r--r--src/cpu/simple/timing.hh8
-rw-r--r--src/cpu/translation.hh6
2 files changed, 14 insertions, 0 deletions
diff --git a/src/cpu/simple/timing.hh b/src/cpu/simple/timing.hh
index 19a4f818e..a2570abe6 100644
--- a/src/cpu/simple/timing.hh
+++ b/src/cpu/simple/timing.hh
@@ -269,6 +269,14 @@ class TimingSimpleCPU : public BaseSimpleCPU
void completeDataAccess(PacketPtr pkt);
void advanceInst(Fault fault);
+ /** This function is used by the page table walker to determine if it could
+ * translate the a pending request or if the underlying request has been
+ * squashed. This always returns false for the simple timing CPU as it never
+ * executes any instructions speculatively.
+ * @ return Is the current instruction squashed?
+ */
+ bool isSquashed() const { return false; }
+
/**
* Print state of address in memory system via PrintReq (for
* debugging).
diff --git a/src/cpu/translation.hh b/src/cpu/translation.hh
index b6bc2182c..90fffa03d 100644
--- a/src/cpu/translation.hh
+++ b/src/cpu/translation.hh
@@ -259,6 +259,12 @@ class DataTranslation : public BaseTLB::Translation
}
delete this;
}
+
+ bool
+ squashed() const
+ {
+ return xc->isSquashed();
+ }
};
#endif // __CPU_TRANSLATION_HH__