Merge yet again with the main repository.

13 files changed, 27 insertions, 30 deletions

diff --git a/src/cpu/base.hh b/src/cpu/base.hh
index cf647daaa..a4ffb4716 100644
--- a/src/cpu/base.hh
+++ b/src/cpu/base.hh
@@ -284,17 +284,16 @@ class BaseCPU : public MemObject
     void enableFunctionTrace();
     void traceFunctionsInternal(Addr pc);
 
-  protected:
+  private:
+    static std::vector<BaseCPU *> cpuList;   //!< Static global cpu list
+
+  public:
     void traceFunctions(Addr pc)
     {
         if (functionTracingEnabled)
             traceFunctionsInternal(pc);
     }
 
-  private:
-    static std::vector<BaseCPU *> cpuList;   //!< Static global cpu list
-
-  public:
     static int numSimulatedCPUs() { return cpuList.size(); }
     static Counter numSimulatedInstructions()
     {
diff --git a/src/cpu/inorder/resources/mult_div_unit.cc b/src/cpu/inorder/resources/mult_div_unit.cc
index 0ff05252c..ab0081787 100644
--- a/src/cpu/inorder/resources/mult_div_unit.cc
+++ b/src/cpu/inorder/resources/mult_div_unit.cc
@@ -299,6 +299,7 @@ MultDivUnit::exeMulDiv(int slot_num)
     }    
 
     mult_div_req->setProcessing(false);
+    cpu->wakeCPU();
 }
 
 void
diff --git a/src/cpu/o3/commit_impl.hh b/src/cpu/o3/commit_impl.hh
index c481d7b9c..b6a4c0387 100644
--- a/src/cpu/o3/commit_impl.hh
+++ b/src/cpu/o3/commit_impl.hh
@@ -51,6 +51,7 @@
 #include "config/use_checker.hh"
 #include "cpu/o3/commit.hh"
 #include "cpu/o3/thread_state.hh"
+#include "cpu/base.hh"
 #include "cpu/exetrace.hh"
 #include "cpu/timebuf.hh"
 #include "debug/Activity.hh"
@@ -987,6 +988,8 @@ DefaultCommit<Impl>::commitInsts()
                 // Updates misc. registers.
                 head_inst->updateMiscRegs();
 
+                cpu->traceFunctions(pc[tid].instAddr());
+
                 TheISA::advancePC(pc[tid], head_inst->staticInst);
 
                 // Keep track of the last sequence number commited
diff --git a/src/cpu/o3/decode_impl.hh b/src/cpu/o3/decode_impl.hh
index 3def971e9..985e92826 100644
--- a/src/cpu/o3/decode_impl.hh
+++ b/src/cpu/o3/decode_impl.hh
@@ -446,10 +446,6 @@ void
 DefaultDecode<Impl>::sortInsts()
 {
     int insts_from_fetch = fromFetch->size;
-#ifdef DEBUG
-    for (ThreadID tid = 0; tid < numThreads; tid++)
-        assert(insts[tid].empty());
-#endif
     for (int i = 0; i < insts_from_fetch; ++i) {
         insts[fromFetch->insts[i]->threadNumber].push(fromFetch->insts[i]);
     }
diff --git a/src/cpu/o3/iew_impl.hh b/src/cpu/o3/iew_impl.hh
index 9c4b1068d..92c8875e4 100644
--- a/src/cpu/o3/iew_impl.hh
+++ b/src/cpu/o3/iew_impl.hh
@@ -1340,10 +1340,10 @@ DefaultIEW<Impl>::executeInsts()
                 fetchRedirect[tid] = true;
 
                 DPRINTF(IEW, "Execute: Branch mispredict detected.\n");
-                DPRINTF(IEW, "Predicted target was PC:%#x, NPC:%#x.\n",
-                        inst->predInstAddr(), inst->predNextInstAddr());
+                DPRINTF(IEW, "Predicted target was PC: %s.\n",
+                        inst->readPredTarg());
                 DPRINTF(IEW, "Execute: Redirecting fetch to PC: %s.\n",
-                        inst->pcState(), inst->nextInstAddr());
+                        inst->pcState());
                 // If incorrect, then signal the ROB that it must be squashed.
                 squashDueToBranch(inst, tid);
 
diff --git a/src/cpu/o3/rename_impl.hh b/src/cpu/o3/rename_impl.hh
index 4106bbef9..04935604e 100644
--- a/src/cpu/o3/rename_impl.hh
+++ b/src/cpu/o3/rename_impl.hh
@@ -766,10 +766,6 @@ void
 DefaultRename<Impl>::sortInsts()
 {
     int insts_from_decode = fromDecode->size;
-#ifdef DEBUG
-    for (ThreadID tid = 0; tid < numThreads; tid++)
-        assert(insts[tid].empty());
-#endif
     for (int i = 0; i < insts_from_decode; ++i) {
         DynInstPtr inst = fromDecode->insts[i];
         insts[inst->threadNumber].push_back(inst);
diff --git a/src/cpu/pc_event.cc b/src/cpu/pc_event.cc
index a07d787f0..9cf63f7d3 100644
--- a/src/cpu/pc_event.cc
+++ b/src/cpu/pc_event.cc
@@ -83,7 +83,9 @@ PCEventQueue::schedule(PCEvent *event)
 bool
 PCEventQueue::doService(ThreadContext *tc)
 {
-    Addr pc = tc->instAddr() & ~0x3;
+    // This will fail to break on Alpha PALcode addresses, but that is
+    // a rare use case.
+    Addr pc = tc->instAddr();
     int serviced = 0;
     range_t range = equal_range(pc);
     for (iterator i = range.first; i != range.second; ++i) {
@@ -91,7 +93,7 @@ PCEventQueue::doService(ThreadContext *tc)
         // another event.  This for example, prevents two invocations
         // of the SkipFuncEvent.  Maybe we should have separate PC
         // event queues for each processor?
-        if (pc != (tc->instAddr() & ~0x3))
+        if (pc != tc->instAddr())
             continue;
 
         DPRINTF(PCEvent, "PC based event serviced at %#x: %s\n",
diff --git a/src/cpu/testers/directedtest/DirectedGenerator.hh b/src/cpu/testers/directedtest/DirectedGenerator.hh
index 904dcf399..c156efff0 100644
--- a/src/cpu/testers/directedtest/DirectedGenerator.hh
+++ b/src/cpu/testers/directedtest/DirectedGenerator.hh
@@ -43,7 +43,7 @@ class DirectedGenerator : public SimObject
     virtual ~DirectedGenerator() {}
     
     virtual bool initiate() = 0;
-    virtual void performCallback(uint proc, Addr address) = 0;
+    virtual void performCallback(uint32_t proc, Addr address) = 0;
     
     void setDirectedTester(RubyDirectedTester* directed_tester);
     
diff --git a/src/cpu/testers/directedtest/InvalidateGenerator.cc b/src/cpu/testers/directedtest/InvalidateGenerator.cc
index 902c6cc15..4d8271a05 100644
--- a/src/cpu/testers/directedtest/InvalidateGenerator.cc
+++ b/src/cpu/testers/directedtest/InvalidateGenerator.cc
@@ -103,7 +103,7 @@ InvalidateGenerator::initiate()
 }
 
 void 
-InvalidateGenerator::performCallback(uint proc, Addr address)
+InvalidateGenerator::performCallback(uint32_t proc, Addr address)
 {
     assert(m_address == address);  
 
diff --git a/src/cpu/testers/directedtest/InvalidateGenerator.hh b/src/cpu/testers/directedtest/InvalidateGenerator.hh
index 14c47b70b..50db180e3 100644
--- a/src/cpu/testers/directedtest/InvalidateGenerator.hh
+++ b/src/cpu/testers/directedtest/InvalidateGenerator.hh
@@ -49,14 +49,14 @@ class InvalidateGenerator : public DirectedGenerator
     ~InvalidateGenerator();
     
     bool initiate();
-    void performCallback(uint proc, Addr address);
+    void performCallback(uint32_t proc, Addr address);
     
   private:
     InvalidateGeneratorStatus m_status;
     Addr m_address;
-    uint m_active_read_node;
-    uint m_active_inv_node;
-    uint m_addr_increment_size;
+    uint32_t m_active_read_node;
+    uint32_t m_active_inv_node;
+    uint32_t m_addr_increment_size;
 };
 
 #endif //__CPU_DIRECTEDTEST_INVALIDATEGENERATOR_HH__
diff --git a/src/cpu/testers/directedtest/RubyDirectedTester.hh b/src/cpu/testers/directedtest/RubyDirectedTester.hh
index 163c206d8..53c389692 100644
--- a/src/cpu/testers/directedtest/RubyDirectedTester.hh
+++ b/src/cpu/testers/directedtest/RubyDirectedTester.hh
@@ -53,11 +53,11 @@ class RubyDirectedTester : public MemObject
         RubyDirectedTester *tester;
 
       public:
-        CpuPort(const std::string &_name, RubyDirectedTester *_tester, uint _idx)
+        CpuPort(const std::string &_name, RubyDirectedTester *_tester, uint32_t _idx)
             : SimpleTimingPort(_name, _tester), tester(_tester), idx(_idx)
         {}
 
-        uint idx;
+        uint32_t idx;
 
       protected:
         virtual bool recvTiming(PacketPtr pkt);
diff --git a/src/cpu/testers/directedtest/SeriesRequestGenerator.cc b/src/cpu/testers/directedtest/SeriesRequestGenerator.cc
index 43e140178..4cf9aed1c 100644
--- a/src/cpu/testers/directedtest/SeriesRequestGenerator.cc
+++ b/src/cpu/testers/directedtest/SeriesRequestGenerator.cc
@@ -89,7 +89,7 @@ SeriesRequestGenerator::initiate()
 }
 
 void 
-SeriesRequestGenerator::performCallback(uint proc, Addr address)
+SeriesRequestGenerator::performCallback(uint32_t proc, Addr address)
 {
     assert(m_active_node == proc);
     assert(m_address == address);  
diff --git a/src/cpu/testers/directedtest/SeriesRequestGenerator.hh b/src/cpu/testers/directedtest/SeriesRequestGenerator.hh
index 97b632a12..9b1c3e8ba 100644
--- a/src/cpu/testers/directedtest/SeriesRequestGenerator.hh
+++ b/src/cpu/testers/directedtest/SeriesRequestGenerator.hh
@@ -49,13 +49,13 @@ class SeriesRequestGenerator : public DirectedGenerator
     ~SeriesRequestGenerator();
     
     bool initiate();
-    void performCallback(uint proc, Addr address);
+    void performCallback(uint32_t proc, Addr address);
     
   private:
     SeriesRequestGeneratorStatus m_status;
     Addr m_address;
-    uint m_active_node;
-    uint m_addr_increment_size;
+    uint32_t m_active_node;
+    uint32_t m_addr_increment_size;
     bool m_issue_writes;
 };