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author | Nilay Vaish <nilay@cs.wisc.edu> | 2013-01-12 22:09:48 -0600 |
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committer | Nilay Vaish <nilay@cs.wisc.edu> | 2013-01-12 22:09:48 -0600 |
commit | 25ec278a0be5e3e09d396ef5be993e45b766790b (patch) | |
tree | 1e053058f01fd0414c87b989f12c497fe6024f0a /src/cpu | |
parent | fe3fbe624e9524ba5fdc55586e40eaa700c81c78 (diff) | |
download | gem5-25ec278a0be5e3e09d396ef5be993e45b766790b.tar.xz |
x86: Changes to decoder, corrects 9376
The changes made by the changeset 9376 were not quite correct. The patch made
changes to the code which resulted in decoder not getting initialized correctly
when the state was restored from a checkpoint.
This patch adds a startup function to each ISA object. For x86, this function
sets the required state in the decoder. For other ISAs, the function is empty
right now.
Diffstat (limited to 'src/cpu')
-rw-r--r-- | src/cpu/o3/cpu.cc | 3 | ||||
-rw-r--r-- | src/cpu/simple/base.cc | 7 | ||||
-rw-r--r-- | src/cpu/simple/base.hh | 2 | ||||
-rw-r--r-- | src/cpu/simple_thread.cc | 6 | ||||
-rw-r--r-- | src/cpu/simple_thread.hh | 1 |
5 files changed, 19 insertions, 0 deletions
diff --git a/src/cpu/o3/cpu.cc b/src/cpu/o3/cpu.cc index 18c536090..393b9a189 100644 --- a/src/cpu/o3/cpu.cc +++ b/src/cpu/o3/cpu.cc @@ -678,6 +678,9 @@ template <class Impl> void FullO3CPU<Impl>::startup() { + for (int tid = 0; tid < numThreads; ++tid) + isa[tid]->startup(threadContexts[tid]); + fetch.startupStage(); decode.startupStage(); iew.startupStage(); diff --git a/src/cpu/simple/base.cc b/src/cpu/simple/base.cc index 13e08a6cb..4db1c6c10 100644 --- a/src/cpu/simple/base.cc +++ b/src/cpu/simple/base.cc @@ -515,6 +515,13 @@ BaseSimpleCPU::advancePC(Fault fault) } } +void +BaseSimpleCPU::startup() +{ + BaseCPU::startup(); + thread->startup(); +} + /*Fault BaseSimpleCPU::CacheOp(uint8_t Op, Addr EffAddr) { diff --git a/src/cpu/simple/base.hh b/src/cpu/simple/base.hh index 18b97c42f..7e84dcc16 100644 --- a/src/cpu/simple/base.hh +++ b/src/cpu/simple/base.hh @@ -172,6 +172,8 @@ class BaseSimpleCPU : public BaseCPU virtual void regStats(); virtual void resetStats(); + virtual void startup(); + // number of simulated instructions Counter numInst; Counter startNumInst; diff --git a/src/cpu/simple_thread.cc b/src/cpu/simple_thread.cc index 9cf8da7b4..77569aa68 100644 --- a/src/cpu/simple_thread.cc +++ b/src/cpu/simple_thread.cc @@ -143,6 +143,12 @@ SimpleThread::unserialize(Checkpoint *cp, const std::string §ion) } void +SimpleThread::startup() +{ + isa->startup(tc); +} + +void SimpleThread::dumpFuncProfile() { std::ostream *os = simout.create(csprintf("profile.%s.dat", diff --git a/src/cpu/simple_thread.hh b/src/cpu/simple_thread.hh index 6f1173b7f..d752ed105 100644 --- a/src/cpu/simple_thread.hh +++ b/src/cpu/simple_thread.hh @@ -150,6 +150,7 @@ class SimpleThread : public ThreadState void serialize(std::ostream &os); void unserialize(Checkpoint *cp, const std::string §ion); + void startup(); /*************************************************************** * SimpleThread functions to provide CPU with access to various |