Merge ARM into the head. ARM will compile but may not actually work.

1 files changed, 27 insertions, 3 deletions

diff --git a/src/dev/Ethernet.py b/src/dev/Ethernet.py
index 2beb0d537..d73d56d03 100644
--- a/src/dev/Ethernet.py
+++ b/src/dev/Ethernet.py
@@ -67,6 +67,7 @@ class EtherDevice(PciDevice):
     interface = Port("Ethernet Interrface")
 
 class IGbE(EtherDevice):
+    # Base class for two IGbE adapters listed above
     type = 'IGbE'
     hardware_address = Param.EthernetAddr(NextEthernetAddr,
         "Ethernet Hardware Address")
@@ -80,7 +81,6 @@ class IGbE(EtherDevice):
         "Number of enteries in the rx descriptor cache")
     clock = Param.Clock('500MHz', "Clock speed of the device")
     VendorID = 0x8086
-    DeviceID = 0x1075
     SubsystemID = 0x1008
     SubsystemVendorID = 0x8086
     Status = 0x0000
@@ -98,6 +98,28 @@ class IGbE(EtherDevice):
     InterruptLine = 0x1e
     InterruptPin = 0x01
     BAR0Size = '128kB'
+    wb_delay = Param.Latency('10ns', "delay before desc writeback occurs")
+    fetch_delay = Param.Latency('10ns', "delay before desc fetch occurs")
+    fetch_comp_delay = Param.Latency('10ns', "delay after desc fetch occurs")
+    wb_comp_delay = Param.Latency('10ns', "delay after desc wb occurs")
+    tx_read_delay = Param.Latency('0ns', "delay after tx dma read")
+    rx_write_delay = Param.Latency('0ns', "delay after rx dma read")
+    phy_pid = Param.UInt16("Phy PID that corresponds to device ID")
+    phy_epid = Param.UInt16("Phy EPID that corresponds to device ID")
+
+class IGbE_e1000(IGbE):
+    # Older Intel 8254x based gigabit ethernet adapter
+    # Uses Intel e1000 driver
+    DeviceID = 0x1075
+    phy_pid = 0x02A8
+    phy_epid = 0x0380
+
+class IGbE_igb(IGbE):
+    # Newer Intel 8257x based gigabit ethernet adapter
+    # Uses Intel igb driver and in theory supports packet splitting and LRO
+    DeviceID = 0x10C9
+    phy_pid = 0x0141
+    phy_epid = 0x0CC0
 
 class EtherDevBase(EtherDevice):
     type = 'EtherDevBase'
@@ -153,8 +175,7 @@ class NSGigE(EtherDevBase):
 
 class Sinic(EtherDevBase):
     type = 'Sinic'
-    cxx_namespace = 'Sinic'
-    cxx_class = 'Device'
+    cxx_class = 'Sinic::Device'
 
     rx_max_copy = Param.MemorySize('1514B', "rx max copy")
     tx_max_copy = Param.MemorySize('16kB', "tx max copy")
@@ -164,6 +185,9 @@ class Sinic(EtherDevBase):
     tx_fifo_high_mark = Param.MemorySize('384kB', "tx fifo high threshold")
     tx_fifo_threshold = Param.MemorySize('128kB', "tx fifo low threshold")
     virtual_count = Param.UInt32(1, "Virtualized SINIC")
+    zero_copy_size = Param.UInt32(64, "Bytes to copy if below threshold")
+    zero_copy_threshold = Param.UInt32(256,
+        "Only zero copy above this threshold")
     zero_copy = Param.Bool(False, "Zero copy receive")
     delay_copy = Param.Bool(False, "Delayed copy transmit")
     virtual_addr = Param.Bool(False, "Virtual addressing")