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| author | Ali Saidi <saidi@eecs.umich.edu> | 2008-08-13 17:41:58 -0400 |
|---|---|---|
| committer | Ali Saidi <saidi@eecs.umich.edu> | 2008-08-13 17:41:58 -0400 |
| commit | 6248e12704275bf4cc88f1743bb3a4bff7adcf9f (patch) | |
| tree | 7c85da7cb7e7148f82c474776e7dac89de7c8093 /src/dev/Ethernet.py | |
| parent | 549c43b2d0cd2411f7c8eda3f89ce1fd695c17e9 (diff) | |
| download | gem5-6248e12704275bf4cc88f1743bb3a4bff7adcf9f.tar.xz | |
Add the ability to specify a think time before descriptor fetch/writeback starts/ends as well as after read/write dmas
Diffstat (limited to 'src/dev/Ethernet.py')
| -rw-r--r-- | src/dev/Ethernet.py | 7 |
1 files changed, 7 insertions, 0 deletions
diff --git a/src/dev/Ethernet.py b/src/dev/Ethernet.py index 2beb0d537..01384b32b 100644 --- a/src/dev/Ethernet.py +++ b/src/dev/Ethernet.py @@ -98,6 +98,13 @@ class IGbE(EtherDevice): InterruptLine = 0x1e InterruptPin = 0x01 BAR0Size = '128kB' + wb_delay = Param.Latency('10ns', "delay before desc writeback occurs") + fetch_delay = Param.Latency('10ns', "delay before desc fetch occurs") + fetch_comp_delay = Param.Latency('10ns', "delay after desc fetch occurs") + wb_comp_delay = Param.Latency('10ns', "delay after desc wb occurs") + tx_read_delay = Param.Latency('0ns', "delay after tx dma read") + rx_write_delay = Param.Latency('0ns', "delay after rx dma read") + class EtherDevBase(EtherDevice): type = 'EtherDevBase' |