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author | Giacomo Travaglini <giacomo.travaglini@arm.com> | 2018-08-30 16:43:02 +0100 |
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committer | Giacomo Travaglini <giacomo.travaglini@arm.com> | 2018-09-10 10:24:10 +0000 |
commit | 579443c64fd176ec2af4c7f38b3d37484ad21ffa (patch) | |
tree | 30fef6eda22a6ea0e7b334c59a6ca62e06e94850 /src/dev/arm/Gic.py | |
parent | 4c9ba9cd2925c83889c6388b4f5a15820bd9986b (diff) | |
download | gem5-579443c64fd176ec2af4c7f38b3d37484ad21ffa.tar.xz |
dev-arm: Factory SimObject for generating ArmInterruptPin
With this patch the python ArmInterruptPin SimObject matches to the
C++ ArmInterruptPinGen. The latter is in charge of generating
the ArmInterruptPin (which is not a SimObject anymore).
This is meant to ease the generation of ArmInterruptPins: by
not being SimObjects we are not forced to instantiate them
in the configuration script; we can generate them dynamically
instead throughout simulation.
Change-Id: I917d73a26168447221f5993c8ae975ee3771e3bf
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/12401
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Diffstat (limited to 'src/dev/arm/Gic.py')
-rw-r--r-- | src/dev/arm/Gic.py | 4 |
1 files changed, 3 insertions, 1 deletions
diff --git a/src/dev/arm/Gic.py b/src/dev/arm/Gic.py index 5f756639e..4cc661f0b 100644 --- a/src/dev/arm/Gic.py +++ b/src/dev/arm/Gic.py @@ -52,6 +52,7 @@ class BaseGic(PioDevice): class ArmInterruptPin(SimObject): type = 'ArmInterruptPin' cxx_header = "dev/arm/base_gic.hh" + cxx_class = "ArmInterruptPinGen" abstract = True platform = Param.Platform(Parent.any, "Platform with interrupt controller") @@ -60,11 +61,12 @@ class ArmInterruptPin(SimObject): class ArmSPI(ArmInterruptPin): type = 'ArmSPI' cxx_header = "dev/arm/base_gic.hh" + cxx_class = "ArmSPIGen" class ArmPPI(ArmInterruptPin): type = 'ArmPPI' cxx_header = "dev/arm/base_gic.hh" - + cxx_class = "ArmPPIGen" class Pl390(BaseGic): type = 'Pl390' |