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authorAndreas Hansson <andreas.hansson@arm.com>2012-02-14 14:15:30 -0500
committerAndreas Hansson <andreas.hansson@arm.com>2012-02-14 14:15:30 -0500
commit6cf9f182f678e4ddf2a2b98a5093a7418353217c (patch)
tree9de2665814818b7ce04cf7b2c85cc907b71a3581 /src/dev/arm
parentac91f90145f824b202d79a9e275fc5cee1071159 (diff)
downloadgem5-6cf9f182f678e4ddf2a2b98a5093a7418353217c.tar.xz
MEM: Fix residual bus ports and make them master/slave
This patch cleans up a number of remaining uses of bus.port which is now split into bus.master and bus.slave. The only non-trivial change is the memtest where the level building now has to be aware of the role of the ports used in the previous level.
Diffstat (limited to 'src/dev/arm')
-rw-r--r--src/dev/arm/RealView.py2
1 files changed, 1 insertions, 1 deletions
diff --git a/src/dev/arm/RealView.py b/src/dev/arm/RealView.py
index e42bc4b94..48a7cf316 100644
--- a/src/dev/arm/RealView.py
+++ b/src/dev/arm/RealView.py
@@ -376,7 +376,7 @@ class VExpress_ELT(RealView):
self.elba_kmi1.pio = bus.master
self.cf_ctrl.pio = bus.master
self.cf_ctrl.config = bus.master
- self.cf_ctrl.dma = bus.port
+ self.cf_ctrl.dma = bus.slave
self.ide.pio = bus.master
self.ide.config = bus.master
self.ide.dma = bus.slave