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| author | Nathan Binkert <nate@binkert.org> | 2010-04-15 16:24:12 -0700 |
|---|---|---|
| committer | Nathan Binkert <nate@binkert.org> | 2010-04-15 16:24:12 -0700 |
| commit | e99828b06a1b694b7aca09682ae2b1be9089af88 (patch) | |
| tree | e106d16b98b45695ffd993e2cd6684919723dc66 /src/dev/i8254xGBe.cc | |
| parent | f7e6f19adabd0ce7e35cea8b5c3b070e2cd26c38 (diff) | |
| download | gem5-e99828b06a1b694b7aca09682ae2b1be9089af88.tar.xz | |
tick: rename Clock namespace to SimClock
Diffstat (limited to 'src/dev/i8254xGBe.cc')
| -rw-r--r-- | src/dev/i8254xGBe.cc | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/src/dev/i8254xGBe.cc b/src/dev/i8254xGBe.cc index ca7e9e67a..2a044ebbe 100644 --- a/src/dev/i8254xGBe.cc +++ b/src/dev/i8254xGBe.cc @@ -693,7 +693,7 @@ IGbE::postInterrupt(IntTypes t, bool now) regs.icr = regs.icr() | t; - Tick itr_interval = Clock::Int::ns * 256 * regs.itr.interval(); + Tick itr_interval = SimClock::Int::ns * 256 * regs.itr.interval(); DPRINTF(EthernetIntr, "EINT: postInterrupt() curTick: %d itr: %d interval: %d\n", curTick, regs.itr.interval(), itr_interval); @@ -801,7 +801,7 @@ IGbE::chkInterrupt() DPRINTF(Ethernet, "Possibly scheduling interrupt because of imr write\n"); if (!interEvent.scheduled()) { - Tick t = curTick + Clock::Int::ns * 256 * regs.itr.interval(); + Tick t = curTick + SimClock::Int::ns * 256 * regs.itr.interval(); DPRINTF(Ethernet, "Scheduling for %d\n", t); schedule(interEvent, t); } |