MEM: Fix residual bus ports and make them master/slave

This patch cleans up a number of remaining uses of bus.port which
is now split into bus.master and bus.slave. The only non-trivial change
is the memtest where the level building now has to be aware of the role
of the ports used in the previous level.

1 files changed, 3 insertions, 3 deletions

diff --git a/src/dev/mips/Malta.py b/src/dev/mips/Malta.py
index ddde06687..23a5e5c8f 100755
--- a/src/dev/mips/Malta.py
+++ b/src/dev/mips/Malta.py
@@ -63,6 +63,6 @@ class Malta(Platform):
     # earlier, since the bus object itself is typically defined at the
     # System level.
     def attachIO(self, bus):
-        self.cchip.pio = bus.port
-        self.io.pio = bus.port
-        self.uart.pio = bus.port
+        self.cchip.pio = bus.master
+        self.io.pio = bus.master
+        self.uart.pio = bus.master