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authorAli Saidi <saidi@eecs.umich.edu>2006-09-18 20:12:45 -0400
committerAli Saidi <saidi@eecs.umich.edu>2006-09-18 20:12:45 -0400
commit17b0e9714d4bde7462d4663899bb9498027f6b40 (patch)
tree464a837d850eb8e076e62d9a6926e9e57516b9d9 /src/dev/pcidev.cc
parentb7d03951268d352254b918fbe1464954828ee8fd (diff)
downloadgem5-17b0e9714d4bde7462d4663899bb9498027f6b40.tar.xz
add boiler plate intel nic code
src/SConscript: add intel nic to sconscript src/dev/pcidev.cc: fix bug with subsystemid value src/python/m5/objects/Ethernet.py: add intel nic to ethernet.py src/python/m5/objects/Ide.py: src/python/m5/objects/Pci.py: Move config_latency into pci where it belogs --HG-- extra : convert_revision : 7163aaf7b4098496518b0910cef62f2ce3dd574d
Diffstat (limited to 'src/dev/pcidev.cc')
-rw-r--r--src/dev/pcidev.cc2
1 files changed, 1 insertions, 1 deletions
diff --git a/src/dev/pcidev.cc b/src/dev/pcidev.cc
index 8ea22cb24..c3b83f448 100644
--- a/src/dev/pcidev.cc
+++ b/src/dev/pcidev.cc
@@ -405,7 +405,7 @@ CREATE_SIM_OBJECT(PciConfigData)
data->config.baseAddr[5] = htole(BAR5);
data->config.cardbusCIS = htole(CardbusCIS);
data->config.subsystemVendorID = htole(SubsystemVendorID);
- data->config.subsystemID = htole(SubsystemVendorID);
+ data->config.subsystemID = htole(SubsystemID);
data->config.expansionROM = htole(ExpansionROM);
data->config.interruptLine = htole(InterruptLine);
data->config.interruptPin = htole(InterruptPin);