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| author | Gabe Black <gblack@eecs.umich.edu> | 2009-02-01 00:26:10 -0800 |
|---|---|---|
| committer | Gabe Black <gblack@eecs.umich.edu> | 2009-02-01 00:26:10 -0800 |
| commit | 70cd5bfce5549495c6e969fa509bfd5f56190e10 (patch) | |
| tree | 0d5bf42d04a037195dd9ea97b4dfbe3054cdb8d7 /src/dev/x86/SouthBridge.py | |
| parent | f1b43b39a764645c8e15b66a1a01d404f03c8307 (diff) | |
| download | gem5-70cd5bfce5549495c6e969fa509bfd5f56190e10.tar.xz | |
X86: Configure the first PCI interrupt.
Diffstat (limited to 'src/dev/x86/SouthBridge.py')
| -rw-r--r-- | src/dev/x86/SouthBridge.py | 3 |
1 files changed, 2 insertions, 1 deletions
diff --git a/src/dev/x86/SouthBridge.py b/src/dev/x86/SouthBridge.py index 8d766471e..d89ed9dc6 100644 --- a/src/dev/x86/SouthBridge.py +++ b/src/dev/x86/SouthBridge.py @@ -87,7 +87,8 @@ class SouthBridge(SimObject): ide.BAR3LegacyIO = True ide.BAR4 = 1 ide.Command = 1 - ide.InterruptLine = 20 + ide.InterruptLine = 14 + ide.InterruptPin = 1 def attachIO(self, bus): # Route interupt signals |