summaryrefslogtreecommitdiff
path: root/src/dev
diff options
context:
space:
mode:
authorAnouk Van Laer <anouk.vanlaer@arm.com>2018-09-27 16:49:30 +0100
committerGiacomo Travaglini <giacomo.travaglini@arm.com>2019-01-04 13:24:40 +0000
commitb5e0a8f19ad5fa3d320b890d416d41f65de8707e (patch)
treee7da2945276e323cb778d20f414f3bedcfc85b47 /src/dev
parent8a9e0079e7fc89c7abbf7d360cd1707d11cd3df0 (diff)
downloadgem5-b5e0a8f19ad5fa3d320b890d416d41f65de8707e.tar.xz
dev-arm: Added unimplemented GICv2 GICC_DIR
This GICC CPU register is not implemented but just gives a warning. Change-Id: I7630aa1df78dde5cf84a87e26cd580b00b283673 Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-by: Anouk Van Laer <anouk.vanlaer@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/15275 Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Diffstat (limited to 'src/dev')
-rw-r--r--src/dev/arm/gic_v2.cc3
-rw-r--r--src/dev/arm/gic_v2.hh1
2 files changed, 4 insertions, 0 deletions
diff --git a/src/dev/arm/gic_v2.cc b/src/dev/arm/gic_v2.cc
index 293c72f1f..1e58718f9 100644
--- a/src/dev/arm/gic_v2.cc
+++ b/src/dev/arm/gic_v2.cc
@@ -622,6 +622,9 @@ GicV2::writeCpu(ContextID ctx, Addr daddr, uint32_t data)
case GICC_APR3:
warn("GIC APRn write ignored because not implemented: %#x\n", daddr);
break;
+ case GICC_DIR:
+ warn("GIC DIR write ignored because not implemented: %#x\n", daddr);
+ break;
default:
panic("Tried to write Gic cpu at offset %#x\n", daddr);
break;
diff --git a/src/dev/arm/gic_v2.hh b/src/dev/arm/gic_v2.hh
index 4afad89f6..49465ad56 100644
--- a/src/dev/arm/gic_v2.hh
+++ b/src/dev/arm/gic_v2.hh
@@ -110,6 +110,7 @@ class GicV2 : public BaseGic, public BaseGicRegisters
GICC_APR2 = 0xd8, // active priority register 2
GICC_APR3 = 0xdc, // active priority register 3
GICC_IIDR = 0xfc, // cpu interface id register
+ GICC_DIR = 0x1000, // deactive interrupt register
};
static const int SGI_MAX = 16; // Number of Software Gen Interrupts