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| author | Gabe Black <gabeblack@google.com> | 2018-10-13 00:54:32 -0700 |
|---|---|---|
| committer | Gabe Black <gabeblack@google.com> | 2019-01-16 20:27:47 +0000 |
| commit | cf0f625b47a8e0334fc3fe8c0c2cdf5aaaf3389e (patch) | |
| tree | 75505d60b69951ec0a99ca82e8621803c95d921d /src/dev | |
| parent | 0c4515ce1ff2a4e40d243df734af2a67cb8b1ad1 (diff) | |
| download | gem5-cf0f625b47a8e0334fc3fe8c0c2cdf5aaaf3389e.tar.xz | |
cpu: dev: sim: gpu-compute: Banish some ISA specific register types.
These types are IntReg, FloatReg, FloatRegBits, and MiscReg. There are
some remaining types, specifically the vector registers and the CCReg.
I'm less familiar with these new types of registers, and so will look
at getting rid of them at some later time.
Change-Id: Ide8f76b15c531286f61427330053b44074b8ac9b
Reviewed-on: https://gem5-review.googlesource.com/c/13624
Reviewed-by: Gabe Black <gabeblack@google.com>
Maintainer: Gabe Black <gabeblack@google.com>
Diffstat (limited to 'src/dev')
| -rw-r--r-- | src/dev/arm/generic_timer.cc | 10 | ||||
| -rw-r--r-- | src/dev/arm/generic_timer.hh | 8 |
2 files changed, 9 insertions, 9 deletions
diff --git a/src/dev/arm/generic_timer.cc b/src/dev/arm/generic_timer.cc index 0994f6dd4..396926f40 100644 --- a/src/dev/arm/generic_timer.cc +++ b/src/dev/arm/generic_timer.cc @@ -312,7 +312,7 @@ GenericTimer::createTimers(unsigned cpus) void -GenericTimer::setMiscReg(int reg, unsigned cpu, MiscReg val) +GenericTimer::setMiscReg(int reg, unsigned cpu, RegVal val) { CoreTimers &core(getTimers(cpu)); @@ -417,7 +417,7 @@ GenericTimer::setMiscReg(int reg, unsigned cpu, MiscReg val) } -MiscReg +RegVal GenericTimer::readMiscReg(int reg, unsigned cpu) { CoreTimers &core(getTimers(cpu)); @@ -508,16 +508,16 @@ GenericTimer::readMiscReg(int reg, unsigned cpu) void -GenericTimerISA::setMiscReg(int reg, MiscReg val) +GenericTimerISA::setMiscReg(int reg, RegVal val) { DPRINTF(Timer, "Setting %s := 0x%x\n", miscRegName[reg], val); parent.setMiscReg(reg, cpu, val); } -MiscReg +RegVal GenericTimerISA::readMiscReg(int reg) { - MiscReg value = parent.readMiscReg(reg, cpu); + RegVal value = parent.readMiscReg(reg, cpu); DPRINTF(Timer, "Reading %s as 0x%x\n", miscRegName[reg], value); return value; } diff --git a/src/dev/arm/generic_timer.hh b/src/dev/arm/generic_timer.hh index b3a7e76ff..acd8b3960 100644 --- a/src/dev/arm/generic_timer.hh +++ b/src/dev/arm/generic_timer.hh @@ -223,8 +223,8 @@ class GenericTimer : public ClockedObject void unserialize(CheckpointIn &cp) override; public: - void setMiscReg(int misc_reg, unsigned cpu, ArmISA::MiscReg val); - ArmISA::MiscReg readMiscReg(int misc_reg, unsigned cpu); + void setMiscReg(int misc_reg, unsigned cpu, RegVal val); + RegVal readMiscReg(int misc_reg, unsigned cpu); protected: struct CoreTimers { @@ -286,8 +286,8 @@ class GenericTimerISA : public ArmISA::BaseISADevice GenericTimerISA(GenericTimer &_parent, unsigned _cpu) : parent(_parent), cpu(_cpu) {} - void setMiscReg(int misc_reg, ArmISA::MiscReg val) override; - ArmISA::MiscReg readMiscReg(int misc_reg) override; + void setMiscReg(int misc_reg, RegVal val) override; + RegVal readMiscReg(int misc_reg) override; protected: GenericTimer &parent; |