diff options
| author | Iru Cai <mytbk920423@gmail.com> | 2020-02-11 16:43:31 +0800 |
|---|---|---|
| committer | Iru Cai <mytbk920423@gmail.com> | 2020-02-11 16:43:31 +0800 |
| commit | 1595558f39f6724b3f5bd630c68bcb35fe8bf012 (patch) | |
| tree | b8f2921c0443e71c6977918a24719632c5be62c0 /src/learning_gem5/part2/SimpleObject.py | |
| parent | 98b2d7acc57b664996de528e6d32ae8abaee2b99 (diff) | |
| download | gem5-1595558f39f6724b3f5bd630c68bcb35fe8bf012.tar.xz | |
learning-gem5: memory access example for simple object
Change-Id: I63a68239ac73b2bce3dea5692deac29a3467d27b
Diffstat (limited to 'src/learning_gem5/part2/SimpleObject.py')
| -rw-r--r-- | src/learning_gem5/part2/SimpleObject.py | 5 |
1 files changed, 5 insertions, 0 deletions
diff --git a/src/learning_gem5/part2/SimpleObject.py b/src/learning_gem5/part2/SimpleObject.py index ee7e9aef2..18ae60e3c 100644 --- a/src/learning_gem5/part2/SimpleObject.py +++ b/src/learning_gem5/part2/SimpleObject.py @@ -28,8 +28,13 @@ # Authors: Jason Lowe-Power from m5.params import * +# m5.proxy for Parent +from m5.proxy import * from m5.SimObject import SimObject class SimpleObject(SimObject): type = 'SimpleObject' cxx_header = "learning_gem5/part2/simple_object.hh" + mem_side = MasterPort("memory side port, send requests") + isread = Param.Bool(True, "is it going to read memory") + system = Param.System(Parent.any, "system object") |