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| author | Ani Udipi <ani.udipi@arm.com> | 2013-11-01 11:56:19 -0400 |
|---|---|---|
| committer | Ani Udipi <ani.udipi@arm.com> | 2013-11-01 11:56:19 -0400 |
| commit | ea76f9757668018ad1f2ccb50fd61b9288057913 (patch) | |
| tree | c48c3c071c6cd41ba1a2d81e21b4e1fa79fbfa92 /src/mem/SConscript | |
| parent | 655bf868282ac2d9d6a711167efa936e7057d405 (diff) | |
| download | gem5-ea76f9757668018ad1f2ccb50fd61b9288057913.tar.xz | |
mem: Use the same timing calculation for DRAM read and write
This patch simplifies the DRAM model by re-using the function that
computes the busy and access time for both reads and writes.
Diffstat (limited to 'src/mem/SConscript')
| -rw-r--r-- | src/mem/SConscript | 1 |
1 files changed, 0 insertions, 1 deletions
diff --git a/src/mem/SConscript b/src/mem/SConscript index 02d0aee73..90b49067e 100644 --- a/src/mem/SConscript +++ b/src/mem/SConscript @@ -76,7 +76,6 @@ CompoundFlag('Bus', ['BaseBus', 'BusAddrRanges', 'CoherentBus', DebugFlag('Bridge') DebugFlag('CommMonitor') DebugFlag('DRAM') -DebugFlag('DRAMWR') DebugFlag('LLSC') DebugFlag('MMU') DebugFlag('MemoryAccess') |