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| author | Erfan Azarkhish <erfan.azarkhish@unibo.it> | 2015-11-03 12:17:56 -0600 |
|---|---|---|
| committer | Erfan Azarkhish <erfan.azarkhish@unibo.it> | 2015-11-03 12:17:56 -0600 |
| commit | 1530e1a690a7d3c1b028e59d2fa37c88df8e47df (patch) | |
| tree | 7b8c62718c14e44e5636ccf4debe1d6180a3f4a9 /src/mem/SConscript | |
| parent | 100cbc9cf63af46697f129c9c10f0cc80ff7db9d (diff) | |
| download | gem5-1530e1a690a7d3c1b028e59d2fa37c88df8e47df.tar.xz | |
mem: hmc: adds controller
This patch models a simple HMC Controller. It simply schedules the incoming
packets to HMC Serial Links using a round robin mechanism. This patch should
be applied in series with other patches modeling a complete HMC device.
Committed by: Nilay Vaish <nilay@cs.wisc.edu>
Diffstat (limited to 'src/mem/SConscript')
| -rw-r--r-- | src/mem/SConscript | 3 |
1 files changed, 3 insertions, 0 deletions
diff --git a/src/mem/SConscript b/src/mem/SConscript index 404f4a90f..3b65131a2 100644 --- a/src/mem/SConscript +++ b/src/mem/SConscript @@ -42,6 +42,7 @@ SimObject('ExternalSlave.py') SimObject('MemObject.py') SimObject('SimpleMemory.py') SimObject('XBar.py') +SimObject('HMCController.py') Source('abstract_mem.cc') Source('addr_mapper.cc') @@ -64,6 +65,7 @@ Source('snoop_filter.cc') Source('stack_dist_calc.cc') Source('tport.cc') Source('xbar.cc') +Source('hmc_controller.cc') if env['TARGET_ISA'] != 'null': Source('fs_translating_port_proxy.cc') @@ -101,6 +103,7 @@ DebugFlag('MemoryAccess') DebugFlag('PacketQueue') DebugFlag('StackDist') DebugFlag("DRAMSim2") +DebugFlag('HMCController') DebugFlag("MemChecker") DebugFlag("MemCheckerMonitor") |