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| author | Andrew Bardsley <Andrew.Bardsley@arm.com> | 2014-10-16 05:49:56 -0400 |
|---|---|---|
| committer | Andrew Bardsley <Andrew.Bardsley@arm.com> | 2014-10-16 05:49:56 -0400 |
| commit | d6732895a5c2e81da47ada339b5d9269c02e5e8b (patch) | |
| tree | c8f1f235e96e76946dde6b914a903b5dd74d170c /src/mem/SConscript | |
| parent | 83f7e7afaf962a6f7967c3ace00a85c58508e2e9 (diff) | |
| download | gem5-d6732895a5c2e81da47ada339b5d9269c02e5e8b.tar.xz | |
mem: Add ExternalMaster and ExternalSlave ports
This patch adds two MemoryObject's: ExternalMaster and ExternalSlave.
Each object has a single port which can be bound to an externally-
provided bridge to a port of another simulation system at
initialisation.
Diffstat (limited to 'src/mem/SConscript')
| -rw-r--r-- | src/mem/SConscript | 5 |
1 files changed, 5 insertions, 0 deletions
diff --git a/src/mem/SConscript b/src/mem/SConscript index 6d225385b..e7d2c1bac 100644 --- a/src/mem/SConscript +++ b/src/mem/SConscript @@ -40,6 +40,8 @@ SimObject('AbstractMemory.py') SimObject('AddrMapper.py') SimObject('Bridge.py') SimObject('DRAMCtrl.py') +SimObject('ExternalMaster.py') +SimObject('ExternalSlave.py') SimObject('MemObject.py') SimObject('SimpleMemory.py') SimObject('XBar.py') @@ -50,6 +52,8 @@ Source('bridge.cc') Source('coherent_xbar.cc') Source('drampower.cc') Source('dram_ctrl.cc') +Source('external_master.cc') +Source('external_slave.cc') Source('mem_object.cc') Source('mport.cc') Source('noncoherent_xbar.cc') @@ -88,6 +92,7 @@ DebugFlag('CommMonitor') DebugFlag('DRAM') DebugFlag('DRAMPower') DebugFlag('DRAMState') +DebugFlag('ExternalPort') DebugFlag('LLSC') DebugFlag('MMU') DebugFlag('MemoryAccess') |