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| author | Andreas Hansson <andreas.hansson@arm.com> | 2012-09-18 10:30:02 -0400 |
|---|---|---|
| committer | Andreas Hansson <andreas.hansson@arm.com> | 2012-09-18 10:30:02 -0400 |
| commit | 7c55464aac2bcab15699e563f18a7d3d565d949a (patch) | |
| tree | bb507025ea2dc209b9d80367665ea3af682b4146 /src/mem/SimpleMemory.py | |
| parent | d1f3a3b91a2370c5e8fae2951a3ee6231158d4f4 (diff) | |
| download | gem5-7c55464aac2bcab15699e563f18a7d3d565d949a.tar.xz | |
Mem: Add a maximum bandwidth to SimpleMemory
This patch makes a minor addition to the SimpleMemory by enforcing a
maximum data rate. The bandwidth is configurable, and a reasonable
value (12.8GB/s) has been choosen as the default.
The changes do add some complexity to the SimpleMemory, but they
should definitely be justifiable as this enables a far more realistic
setup using even this simple memory controller.
The rate regulation is done for reads and writes combined to reflect
the bidirectional data busses used by most (if not all) relevant
memories. Moreover, the regulation is done per packet as opposed to
long term, as it is the short term data rate (data bus width times
frequency) that is the limiting factor.
A follow-up patch bumps the stats for the regressions.
Diffstat (limited to 'src/mem/SimpleMemory.py')
| -rw-r--r-- | src/mem/SimpleMemory.py | 4 |
1 files changed, 4 insertions, 0 deletions
diff --git a/src/mem/SimpleMemory.py b/src/mem/SimpleMemory.py index c47d04222..9361b45d8 100644 --- a/src/mem/SimpleMemory.py +++ b/src/mem/SimpleMemory.py @@ -47,3 +47,7 @@ class SimpleMemory(AbstractMemory): port = SlavePort("Slave ports") latency = Param.Latency('30ns', "Request to response latency") latency_var = Param.Latency('0ns', "Request to response latency variance") + # The memory bandwidth limit default is set to 12.8GB/s which is + # representative of a x64 DDR3-1600 channel. + bandwidth = Param.MemoryBandwidth('12.8GB/s', + "Combined read and write bandwidth") |