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| author | Andreas Hansson <andreas.hansson@arm.com> | 2015-08-21 07:03:23 -0400 |
|---|---|---|
| committer | Andreas Hansson <andreas.hansson@arm.com> | 2015-08-21 07:03:23 -0400 |
| commit | ddfa96cf455ba4a287930942514cdf0f7f2afa77 (patch) | |
| tree | 89eddf6ab0ec6f4660629b45b1b7cff7df6ca82c /src/mem/cache/cache.cc | |
| parent | d71a0d790d8d1113480c5a57d7bfbb9b7d0d0037 (diff) | |
| download | gem5-ddfa96cf455ba4a287930942514cdf0f7f2afa77.tar.xz | |
mem: Add explicit Cache subclass and make BaseCache abstract
Open up for other subclasses to BaseCache and transition to using the
explicit Cache subclass.
--HG--
rename : src/mem/cache/BaseCache.py => src/mem/cache/Cache.py
Diffstat (limited to 'src/mem/cache/cache.cc')
| -rw-r--r-- | src/mem/cache/cache.cc | 11 |
1 files changed, 9 insertions, 2 deletions
diff --git a/src/mem/cache/cache.cc b/src/mem/cache/cache.cc index 2426a0636..911785479 100644 --- a/src/mem/cache/cache.cc +++ b/src/mem/cache/cache.cc @@ -63,8 +63,8 @@ #include "mem/cache/prefetch/base.hh" #include "sim/sim_exit.hh" -Cache::Cache(const Params *p) - : BaseCache(p), +Cache::Cache(const CacheParams *p) + : BaseCache(p, p->system->cacheLineSize()), tags(p->tags), prefetcher(p->prefetcher), doFastWrites(true), @@ -2382,6 +2382,13 @@ CpuSidePort::CpuSidePort(const std::string &_name, Cache *_cache, { } +Cache* +CacheParams::create() +{ + assert(tags); + + return new Cache(this); +} /////////////// // // MemSidePort |