diff options
| author | Nikos Nikoleris <nikos.nikoleris@arm.com> | 2016-10-10 14:40:10 +0100 |
|---|---|---|
| committer | Nikos Nikoleris <nikos.nikoleris@arm.com> | 2018-10-18 09:39:50 +0000 |
| commit | e57d8f2d897bc26aade774e090842367e38e974b (patch) | |
| tree | 21ca8d61a261dd1543649d1fdd266bc57e762725 /src/mem/cache/cache.hh | |
| parent | 0ac40753c3dba5fa647006455238acad0cb3e3ec (diff) | |
| download | gem5-e57d8f2d897bc26aade774e090842367e38e974b.tar.xz | |
mem: Restructure whole-line writes to simplify write merging
This patch changes how we deal with whole-line writes their
responses. With these changes, we use the MSHR tracking to determine
if a whole-line is written, and on a fill we simply handle the
invalidation response, with the actual writes taking place as part of
satisfying the CPU-side hit.
Change-Id: I9a18e41a95db3c20b97f8bca7d95ff33d35a578b
Reviewed-on: https://gem5-review.googlesource.com/c/12905
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>
Diffstat (limited to 'src/mem/cache/cache.hh')
| -rw-r--r-- | src/mem/cache/cache.hh | 3 |
1 files changed, 2 insertions, 1 deletions
diff --git a/src/mem/cache/cache.hh b/src/mem/cache/cache.hh index f8eccfee6..588e7b94e 100644 --- a/src/mem/cache/cache.hh +++ b/src/mem/cache/cache.hh @@ -152,7 +152,8 @@ class Cache : public BaseCache PacketPtr cleanEvictBlk(CacheBlk *blk); PacketPtr createMissPacket(PacketPtr cpu_pkt, CacheBlk *blk, - bool needsWritable) const override; + bool needs_writable, + bool is_whole_line_write) const override; /** * Send up a snoop request and find cached copies. If cached copies are |