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| author | Andreas Hansson <andreas.hansson@arm.com> | 2014-09-27 09:08:29 -0400 |
|---|---|---|
| committer | Andreas Hansson <andreas.hansson@arm.com> | 2014-09-27 09:08:29 -0400 |
| commit | de62aedabc96e7492c40bbc4468ba42b3274bfd6 (patch) | |
| tree | e68dae6dd1f3da0e7d2dcf3e946728c46e63bbce /src/mem/cache/cache_impl.hh | |
| parent | 71d5f03175b3a684b94bbc515ebc02e2b493b7cf (diff) | |
| download | gem5-de62aedabc96e7492c40bbc4468ba42b3274bfd6.tar.xz | |
misc: Fix a bunch of minor issues identified by static analysis
Add some missing initialisation, and fix a handful benign resource
leaks (including some false positives).
Diffstat (limited to 'src/mem/cache/cache_impl.hh')
| -rw-r--r-- | src/mem/cache/cache_impl.hh | 3 |
1 files changed, 3 insertions, 0 deletions
diff --git a/src/mem/cache/cache_impl.hh b/src/mem/cache/cache_impl.hh index e4a6f3c24..5cfe7c0cf 100644 --- a/src/mem/cache/cache_impl.hh +++ b/src/mem/cache/cache_impl.hh @@ -917,6 +917,9 @@ Cache<TagStore>::recvAtomic(PacketPtr pkt) if (pkt->cmd == MemCmd::WriteInvalidateReq) { memSidePort->sendAtomic(pkt); // complete writeback if (isTopLevel) { + // @todo Static analysis suggests this can actually happen + assert(blk); + // top level caches allocate and write the data assert(blk->isDirty()); assert(!blk->isWritable()); |